The invention discloses an ISA instruction format splicing method based on SystemRDL, and relates to the technical field of ISA instruction splicing, which comprises the following steps: establishing
bit field mapping, analyzing operation code and
operand information, definition field attribute, operation code field bit width of 7-10 bits, and immediate number field of 8-20 bits; instruction behaviors are expanded, operation logic and
time sequence constraints are supplemented, and automatic assembling is carried out; the attribute of an
operand is defined, the bit width of a register is 16-64 bits, and the bit width of an immediate digit is 1 bit to the maximum support width; splicing according to function classification, and setting corresponding
bit field structures for arithmetic operation, memory access and control instructions;
processing macro and pseudo instructions, decomposing and sequencing the
macro instructions, and mapping the pseudo instructions; and scanning for three times to generate assembler codes, and sequentially analyzing, associating, integrating and outputting. According to the method, the instruction assembling efficiency and accuracy are improved, the expansibility and compatibility are enhanced,
verification and maintenance are simplified, and
automation and
standardization of processor development are promoted.