126 results about "Macro instruction" patented technology

The processing method to deal with a multifunctional menu of a human input device is applied on a window operating system having plural window application programs. The menu operated on a human input device includes an auto-scroll menu to indicate scrolling function and a multifunctional menu so as to operate plural window application programs in a human interface mode. The multifunctional menu includes macro instruction icons, instruction icons corresponding to the macro instruction icons and a first switching icon for switching to the auto-scroll menu. The auto-scroll menu includes a second switching icon used on the auto-scroll menu for switching to the multifunctional menu.

The invention relates to a method and a system for executing a register type instruction in a RISC (Reduced Instruction-Set Computer) processor. The method comprises the following steps of: 1. if the condition that the available number of used type registers is insufficient when a register type instruction in an assembly code is executed is discovered, generating a macroinstruction corresponding to the register type instruction and replacing the register type instruction by using the macroinstruction; 2. carrying out instruction extraction, decoding, register reading, emission, execution and back-writing on the assembly code in a production line way; when decoding, recognizing whether the current instruction is the macroinstruction or the register type instruction; as for the register type instruction, adding a mark site for indicating the operand type into a register number and generating a complete register number; and when reading the register, reading the register corresponding tothe register number in a type register file appointed by the mark site of the complete register number of the current instruction. The invention can improve the program running performance without the limitation of the number of the specific type physical registers in the processor.

Without letting a user execute a cumbersome judgment of a version, an application program of the most suitable version is installed for data file automatically, thus an automatic activation of the application becomes possible. Firstly, a document file of a readout target is analyzed, a feature point as reserved word of macro instruction is extracted, and a version of an application suited for the document file is distinguished by an extracted feature point. Secondly, it is judged whether an application program of the version distinguished mentioned above is installed already. When found not being installed based on this judgment result, an application program of the version is newly installed.

A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and an N-bit destination register to receive an N-bit result. The N-bit first source register and the N-bit destination register are the N-bit architected general purpose register. An execution unit receives the merge microinstruction and responsively generates the N-bit result to be subsequently written to the N-bit architected general purpose register even though the macroinstruction only instructs the microprocessor to write the 8-bit result into the lower 8 bits of the N-bit architected general purpose register. Specifically, the execution unit directs the 8-bit result into the lower 8 bits of the N-bit result and directs the upper N-8 bits of the N-bit first source register into corresponding upper N-8 bits of the N-bit result.

Techniques for generation of Java™ macro instructions suitable for use in Java™ computing environments are disclosed. As such, the techniques can be implemented in a Java™ virtual machine to efficiently execute Java™ instructions. As will be appreciated, a Java™ macro instruction can be substituted for two or more Java™ Bytecode instructions. This, in turn, reduces the number of Java™ instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java™ macro instruction can be generated for conventional Java™ instruction sequences or sequences of Java™ instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java™ macro instruction. These sequences are typically encountered when Java™ objects are instantiated, during programming loops, and when a local variables are assigned a value.

The invention relates to a script device, a data processing method and an automated testing system based on a multi-terminal mode. The script device communicates with a basic service terminal and includes a master control device, a macroinstruction interpretation device, a script translation device and a data storage device; the script translation device acquires an instruction set script from the data storage device by the master control device and translates script instructions into macroinstruction or operation at a basic service terminal one by one; the macroinstruction interpretation device restores the macroinstruction generated by the script translation device into the operation adapted to the terminal mode of the basic service terminal by communicating with the basic service terminal by the master control device. The same set of the scripts of the invention can adapt to the application program interface of different terminal modes, and the user only needs to maintain one set of the scripts after a test case is designed so as to realize the tests on various terminal modes.

The invention relates to a method and a system for simulating multisystem synchronous numerical-control processing, and belongs to the field of simulating training of numerical-control processing. The method comprises the following steps of customizing a virtual processing environment by a virtual processing system by an operator, and customizing a real processing environment by a real processing system; selecting a numerical-control system panel through a multisystem control platform to carry out numerical-control programming and controlling, encoding a numerical-control instruction, sending to a simulation controller, and enabling the simulation controller to simulate and calculate; on one hand, sending movement parameters of a cutter to the virtual processing system to complete virtual processing; and on the other hand, sending a processing macro instruction to the real processing system, so as to control a machine tool to complete the practical processing of blanks or repairing pieces. The method and the system have the advantages that the design concept is advanced, the function is practical, the cost is low, the deployment is convenient, the system compatibility is good, the group training method is flexible and variable, the processing process is visual and accurate, the human-computer interaction is good, the operation reality of a user is high, the user experience can be obviously changed, and the like.

The invention provides a macro instruction generator for an unmanned aerial vehicle with a variable flying mode and an instruction generation method for the macro instruction generator. The instruction generator comprises a guide instruction generator, a controlled state instruction generator, a state reference value generator and a macro control surface reference instruction generator. Balancing of a mode conversion process is equivalent to the balancing of various combined states in a sequence consisting of tilt angles and desired pitching angles; and in a specific tilt angle and desired pitching angle combined state, iterative optimization balancing is instructed by a cost function, so that balanced values of a state vector and a control vector of the macro control surface are changed stably along with the tilt angle and an air speed instruction. All inner functions of the guide instruction generator, the controlled state instruction generator, the state reference value generator and the macro control surface reference instruction generator are established by adopting a segmental curve fitting method according to a balanced result sequence. The iterative optimization balancing and the curve fitting are realized efficiently and accurately by using matrix laboratory (matlab) math software.

A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation. The load logic is coupled to the paired operation translation logic. The load logic receives the pop-compare micro instruction, and retrieves a first operand from an address in memory, where the address is specified by contents of a register. The register is prescribed by the pop-compare micro instruction. The execution logic is coupled to the load logic. The execution logic receives the first operand, and compares the first operand to a second operand.

A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.

A remote controller apparatus for controlling a broadcast receiving apparatus is provided, in which the remote controller apparatus includes a storage unit, a user interface unit which sequentially receives at least one control instruction relating to controlling the broadcast receiving apparatus, an interface unit which transmits the at least one control instruction received via the user interface unit to the broadcast receiving apparatus, and which receives status information relating to the broadcast receiving apparatus based on the at least one control instruction, and a control unit causes the status information to be stored by the storage unit, and if the instruction relating to setting macro functionality is received via the user interface unit, generates a macro instruction relating to controlling the broadcast receiving apparatus based on the status information and causes the generated macro instruction to be stored by the storage unit.

A printer controller obtains high-speed bitmap generation processing while maintaining flexibility in macro definition when generating bitmap data from a macro-formed data. A processing unit calls macro data from a memory storing macro data to generate bitmap data. The processing unit determines effectiveness of bitmapping the macro instruction, to store into memory the bitmap data only when the bitmapped data is determined effective. Even in case of macro definition having degree of freedom, the data can be retained in a bitmap form. This enables to omit command analysis and expansion next time or after in macro control having flexibility in macro definition.

Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

A method and apparatus for redundant zero micro-operation removal. In one embodiment, the method includes the identification of a predetermined macro-instruction. Once identified, a value associated with a source register operand of the identified macro-instruction is determined. Once determined, the identified macro-instruction is decoded into a first macro operation and a second micro-operation if the determined value is not set. Otherwise, the identified macro-instruction is decoded into a single micro-operation if the determined value is set. Accordingly, the method described prevents the generation of redundant micro-operations that use valuable resources, such as allocation slots, as well as execution units within the processor core.

The invention relates to a processing method used for dressing a grinding wheel, in particular to a grinding wheel dressing method used for slewing support double circular roller path grinding, relating to the field of metal processing. In the dressing method, the rotation motion of the grinding wheel is taken as the main motion to form a principle axis S axis; the horizontal and vertical feeding linear motion of the grinding wheel is driven by the horizontal motion mechanism and the vertical motion mechanism of the grinding wheel to substitute the circular interpolating motion of the grinding wheel to form an X axis and a Z axis; the rotation of the diamond pen is driven by the diamond pen rotation motion mechanism to form a C axis; and the dressing of the whole grinding wheel is realized through the micro-segment dressing of the processing station after discretization, thus being capable of meeting the requirements of multispecies standard grinding wheel dressing functions and having the advantages of stable processing and stable accuracy; in the method, a macro instruction programming method is applied, and is a program compiling mode in which variables can be used for arithmetic operation, logic operation and function mixed operation, thus greatly simplifying program quantity and strengthening the processing and adaptive capabilities of the machine tool.

The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.

A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives an indirect near jump macro instruction, and generates a load-jump micro instruction, where the load-jump micro instruction directs load logic to retrieve an offset and directs the execution logic to generate a target address. The load logic is coupled to the paired operation translation logic and receives the load-jump micro instruction. The load logic retrieves the offset from memory, where the offset indicates a jump destination that is relative to an instruction address corresponding to the indirect near jump macro instruction. The execution logic is coupled to the load logic. The execution logic receives the offset, and employs the instruction address and the offset to generate the target address specifying the jump destination for the near jump operation.

The invention discloses a deep learning processor, and the processor comprises a scheduling module which is used for receiving a data processing request, and analyzing a macro instruction in a targetinstruction set according to the data processing request so as to obtain an analysis result; The convolution calculation module is used for executing a two-dimensional convolution calculation operation corresponding to the analysis result in a three-dimensional convolution pulse array to obtain a data processing result; Wherein the three-dimensional convolution pulse array is obtained by arranginga plurality of operation units according to a multiplication and addition device array construction rule. According to the method, the requirement of convolution calculation for bandwidth can be reduced, the efficiency of convolution calculation is improved, and the processing flow of deep learning is optimized. The invention further discloses the electronic equipment which has the above beneficial effects.