Method and system for executing register type instruction in RISC (Reduced Instruction-Set Computer) processor

A technology of registers and processors, applied in the computer field, can solve problems such as insufficient registers and incomplete data dependence, and achieve the effect of simple implementation and improved performance

Active Publication Date: 2010-12-15
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When data dependence occurs, the order of scheduling instructions can be used to remove the dependence, so that the program can achieve higher efficiency and better performance. However, instruction scheduling cannot completely solve the problems caused by data dependence.
If the previous instruction in the instruction queue has too long

Method used

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  • Method and system for executing register type instruction in RISC (Reduced Instruction-Set Computer) processor
  • Method and system for executing register type instruction in RISC (Reduced Instruction-Set Computer) processor
  • Method and system for executing register type instruction in RISC (Reduced Instruction-Set Computer) processor

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0063] Step S210, when fetching the instruction, fetch the instruction according to the instruction address, and send it to the decoding stage.

[0064] Step S220, when decoding, determine the type of the instruction according to the opcode of the current instruction, and recognize that the current instruction is a macro instruction or a register type instruction, and for the register type instruction, determine the operand type according to the type of the register type instruction, and Add flag bits indicating the operand type to the register number of the register type instruction to generate a complete register number; determine the functional part number of the instruction according to the opcode of the current instruction, and encode the current instruction to generate an internal recognizable by the functional part Opcode encoding.

[0065] The specific implementation manner of step S220 is as follows Figure 4 shown.

[0066] In step S401, the decoding unit determine...

specific Embodiment approach 2

[0078] In a specific implementation manner, the specific steps of step S200 are as follows.

[0079] Step S210', when fetching the instruction, fetch the instruction according to the instruction address, and send it to the decoding stage.

[0080] Step S220', when decoding, determine the type of the instruction according to the opcode of the current instruction, and recognize that the current instruction is a macro instruction or a register type instruction, and for the register type instruction, determine the operand type according to the type of the register type instruction, and Add a flag indicating the operand type to the register number of the register type instruction to generate a complete register number; encode the current instruction to generate an internal opcode code that can be recognized by the functional unit.

[0081] Step S230', when reading registers and transmitting, read the register file corresponding to the register number in the register file of the typ...

Embodiment

[0090] The flow process of a specific embodiment of the method for executing register type instructions in the RISC processor of the present invention is as follows Figure 5 shown.

[0091] In this embodiment, the MIPS floating-point multiply-add instruction madd.f is taken as an example.

[0092] Step S501, when finding a floating-point multiplication-add instruction madd.f in the assembly code, the available number of used floating-point registers will be insufficient, then generate the macro instruction PMAC_F corresponding to the multiplication-add instruction madd.f, so that the macro instruction PMAC_F Replaces the multiply-add instruction madd.f.

[0093] The internal opcode encoding of the macroinstruction PMAC_F is the same as the internal opcode encoding of the floating-point multiply-add instruction madd.f, and the register number of the macroinstruction PMAC_F is a complete register number, including a flag bit indicating the type of register used, which is float...

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PUM

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Abstract

The invention relates to a method and a system for executing a register type instruction in a RISC (Reduced Instruction-Set Computer) processor. The method comprises the following steps of: 1. if the condition that the available number of used type registers is insufficient when a register type instruction in an assembly code is executed is discovered, generating a macroinstruction corresponding to the register type instruction and replacing the register type instruction by using the macroinstruction; 2. carrying out instruction extraction, decoding, register reading, emission, execution and back-writing on the assembly code in a production line way; when decoding, recognizing whether the current instruction is the macroinstruction or the register type instruction; as for the register type instruction, adding a mark site for indicating the operand type into a register number and generating a complete register number; and when reading the register, reading the register corresponding tothe register number in a type register file appointed by the mark site of the complete register number of the current instruction. The invention can improve the program running performance without the limitation of the number of the specific type physical registers in the processor.

Description

technical field [0001] The invention relates to the field of computers, in particular to a method for executing register type instructions in a RISC processor and a system thereof. Background technique [0002] In the design of general-purpose RISC processors, in order to make full use of processor resources, pipelines are generally used. The pipelines are generally divided into fetching (Fetch), decoding (Decode), reading registers and launching (RegisterFile), executing (Execute), writing Back (WriteBack) level five, such as figure 1 shown. [0003] In most instruction sets using RISC, the operand is specified by the register number in the instruction, if the number of registers in the register file is 2 n , then n bits in the instruction are used to address the register. For the distinction between fixed-point registers and floating-point registers, it is judged by the instruction type. Take the MIPS instruction as an example, such as figure 2 As shown, it has three...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38
Inventor 安述倩余磊张浩范东睿
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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