Pop-compare micro instruction for repeat string operations

Abstract

A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation. The load logic is coupled to the paired operation translation logic. The load logic receives the pop-compare micro instruction, and retrieves a first operand from an address in memory, where the address is specified by contents of a register. The register is prescribed by the pop-compare micro instruction. The execution logic is coupled to the load logic. The execution logic receives the first operand, and compares the first operand to a second operand.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60 / 345449, filed on Oct. 23, 2001.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates in general to the field of microelectronics, and more particularly to apparatus in a pipeline microprocessor for efficiently performing string scan and compare operations. [0004] 2. Description of the Related Art [0005] Early microprocessors executed one instruction at a time. Accordingly, each individual instruction was fetched from memory and all of the functions prescribed by the instruction were executed by functional units within the microprocessors until all the functions were completed. At that point, the individual instruction was retired and a next instruction was fetched from memory for execution. [0006] Although execution of program instructions in an early microprocessor was simple to understand, the practical affect of...

AI Technical Summary

Problems solved by technology

Although execution of program instructions in an early microprocessor was simple to understand, the practical affect of their execution was quite slow.

Problems of inefficiently occur when a particular pipeline stage takes too long to perform its prescribed operation.

Although the operations prescribed by many macro instructions can be executed in a single traversal through the pipeline, there remain numerous instructions whose prescribed operations are so complex that they cannot be executed in a single traversal.

Consequently, both of these types of operations cannot be performed during the same pipeline cycle within that particular stage.

Stalling the pipeline for one or more cycles is disadvantageous from a throughput perspective.

And a single load-compare operation results in at least one pipeline stall.

But when string compare macro instructions are employed iteratively many times over, as is typically seen within many application programs, the disadvantages caused by stalls during a single iteration of a string compare operation are furthermore exacerbated in proportion to the number of prescribed iterations.

Any type of operation in a pipeline microprocessor that requires multiple pipeline cycles to accomplish is problematic in that inefficient utilization of the pipeline stages is experienced.

When this inefficient utilization is compounded by iterative situations, the execution speed of a microprocessor suffers.

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