Three-level leadframe for no-lead packages

Abstract

A semiconductor device (700) having a leadframe with a first plurality of segments (110) having a narrow end portion (111) in a first horizontal plane (211) and a wide end portion (112) in a second horizontal plane (212). The leadframe further includes a second plurality of segments (120) having a narrow center portion (121) in the first horizontal plane, at least one wide center portion (122) in the second horizontal plane, and narrow end portions (123) in a third horizontal plane (213), which is located between the first and second planes.

Description

FIELD OF THE INVENTION [0001] The present invention is related in general to the field of semiconductor devices and processes, and more specifically to the structure and material of leadframes for integrated circuit devices. DESCRIPTION OF THE RELATED ART [0002] When the flip-chip technology is used in the assembly of semiconductor devices, in spite of its frequently higher cost compared to wire bonding, it is often required in order to meet demanding performance goals. Among these performance goals are higher numbers of input / output (I / O) terminals, shorter electrical paths for higher speed and frequency, and lower heat dissipation paths for improved thermal performance. These performance goals are driven, for instance, by the pervasive growth of semiconductor products for the wireless and computer peripheral markets. Devices with a need for high frequency performance yet low I / O count include power amplifiers and optical transceivers. [0003] In another trend in the semiconductor i...

AI Technical Summary

Benefits of technology

The invention is a leadframe for assembling semiconductor chips, which includes a first plurality of segments and a second plurality of segments. The first plurality of segments has narrow end portions in a first horizontal plane and wide end portions in a second horizontal plane, while the second plurality of segments has narrow center portions in the first horizontal plane, at least one wide center portion in the second horizontal plane, and narrow end portions in a third horizontal plane. The narrow end portions of the first plurality of segments are attached to interconnection elements on the first plurality of chip contact pads, while the narrow central portions of the second plurality of segments are attached to interconnection elements on the second plurality of chip contact pads. The chip interconnection elements are bumps made of reflowable metal or alloy, preferably tin or tin alloy, or non-reflowable metal or alloy, preferably gold. The invention allows for improved thermal characteristics, low voltage drop of power and ground inputs / outputs, and accommodates low and intermediate I / O counts.

Problems solved by technology

When the flip-chip technology is used in the assembly of semiconductor devices, in spite of its frequently higher cost compared to wire bonding, it is often required in order to meet demanding performance goals.

Most often, however, no-lead packages are based on wire bonding technology.

Only recently have no-lead packages been proposed in the literature for flip-chip assembly; these packages are, however, only suitable for low I / O count (8 to 100 I / O's).

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