System and method for data packet segmentation and reassembly based on clos switching network

A technology for switching networks and data packets, applied in data switching networks, digital transmission systems, transmission systems, etc., can solve problems such as bus efficiency can only reach 50%, increase bus operating frequency, throughput chip bottlenecks, etc., and achieve the working clock The effect of low requirements, improved bus efficiency, and improved throughput

Active Publication Date: 2018-04-20
FENGHUO COMM SCI & TECH CO LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But it will also bring problems: the delay to reach the same OM through different CMs may be different
For 64 bytes, 129 bytes and other packet lengths, the bus efficiency can only reach 50%
In order to meet the throughput requirements of these data packets of a specific length, the chip has to increase the bus operating frequency, which brings a lot of complexity to the entire chip design
If the bus operating frequency cannot be satisfied, the throughput of these specific length packets will become the bottleneck of the chip

Method used

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  • System and method for data packet segmentation and reassembly based on clos switching network
  • System and method for data packet segmentation and reassembly based on clos switching network
  • System and method for data packet segmentation and reassembly based on clos switching network

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Embodiment Construction

[0036] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0037] see figure 2 As shown, the embodiment of the present invention provides a system based on CLOS switching network packet segmentation and reassembly. The CLOS switching network includes several input modules IM, several intermediate modules CM and several output modules OM; each CM Respectively connected to each IM and each OM, each IM includes a composite packet scheduler, a variable-length slice unit, and a routing unit; each OM includes a reassembly unit; where:

[0038] The composite package scheduler includes the queue scheduler, composite package container and raw package cache;

[0039] The queue scheduler is used to combine the data packets originating from the same virtual output queue VOQ and whose packet length is less than the preset value to form a combined package, which is marked with a corresponding mark and sent to the...

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Abstract

The invention discloses a data packet segmentation and recombination system and method based on a CLOS switching network, and relates to the field of communication technology. The CLOS switching network includes several input modules IM, several intermediate modules CM and several output modules OM; each The CM is respectively connected with each IM and each OM; each IM includes a composite packet scheduler, a variable-length slice unit, and a routing unit; each OM includes a reassembly unit. The invention improves the efficiency of the bus, and under the condition of the same bus width and bus operating frequency, can significantly improve the throughput of short packets and special-length packets, and realizes significant improvement of system performance.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a system and method for dividing and reassembling data packets based on a CLOS switching network. Background technique [0002] The cell-based CLOS switching network has the characteristics of non-blocking, expandable and large capacity, and has become the mainstream of switching chips at present. The CLOS switching network includes IM (Input Module, input module), CM (Central Module, intermediate module) and OM (Output Module, output module), which can form a 3-level CLOS structure and can be easily expanded to 5-level CLOS structure. By folding, the functions of IM and OM can be realized in one chip, while the function of CM can be realized in another chip. [0003] The Ethernet data packet (Packet) is variable in length, and the maximum packet length may reach 16,000 bytes. Switching based on data packets in the switch chip will bring a large delay and require a large ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/951H04L47/43
CPCH04L49/9057
Inventor 张伟黄元波
Owner FENGHUO COMM SCI & TECH CO LTD
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