Serial processor and processing method for interpolation device

A technology of serial processing and interpolation processing, which is applied in the field of communication and can solve the problem of large consumption of logic resources

Inactive Publication Date: 2007-11-21
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The advantage of the parallel scheme is that 9 sample data are input in parallel, and 8 sample data are output in parallel after interpolation. The throughput is large and the control logic is simple; the disadvantage is that 16 multipliers and 14 adders are required, and the logic resource consumption is large.

Method used

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  • Serial processor and processing method for interpolation device
  • Serial processor and processing method for interpolation device
  • Serial processor and processing method for interpolation device

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Embodiment Construction

[0028] The specific implementation manners of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Referring to FIG. 4, an interpolation serial processing device according to an embodiment of the present invention is illustrated. As shown in Figure 4, the difference serial processing device includes: a control unit 402, which is used to control the interpolation processing unit to generate sample data, interpolation coefficients and control signals required by the interpolation processing unit, wherein the control unit converts the sample The data and interpolation coefficients are serially input to the interpolation processing unit by beats; and the interpolation processing unit 404 is used to perform multiplication and accumulation calculation on the sample data by using the sample data, interpolation coefficients and control signals from the control unit under the control of the control unit, and Transmit the interpol...

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Abstract

The apparatus comprises: a control unit used for controlling the interpolation processing unit and generating the sample data, interpolation factor and control signal required by the interpolation processing unit; and an interpolation processing unit used for, under the control of the control unit, using the sample data, interpolation factor and control signal to make the multiply and summation calculation for the sample data, and transmitting the processed sample data to the control unit in order to output it.

Description

technical field [0001] The present invention relates to the communication field, and more particularly relates to an interpolator serial processing device and method. Background technique [0002] The interpolation technology is a commonly used code processing technology in a Wideband Code Division Multiple Access (WCDMA) system. In the WCDMA system, different interpolation algorithms can be used to complete interpolation according to performance requirements. The 8TAP interpolation algorithm that the present invention realizes is as follows: [0003] [0004] [0005] [0006] [0007] rounded down, [0008] Among them, z(k) is the interpolated data, y(i) is the original sample data, phase k (i) is the interpolation coefficient (hereinafter abbreviated as p k (i)). [0009] The interpolation process is to calculate the output 8-sample data through the input historical 9-sample data. Among them, the original 9-sample data y(0), y(1), y(2), y(3), y(4), y...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/02H04B1/707H04J13/00
Inventor 陈旭
Owner ZTE CORP
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