Ultrahigh-speed low-jitter multi-phase clock circuit

Abstract

The invention discloses an ultrahigh-speed low-jitter multi-phase clock circuit. The circuit comprises an input clock recovery and duty ratio adjustment module, a phase discriminator module, a charge pump and loop filter module, a variable delay line module, a clock offset error calibration module and a frequency division module, wherein the phase discriminator module is used for detecting a phase relationship between a reference clock and a feedback clock, and correspondingly outputting an 'UP' or 'Down' pulse level to the charge pump; and the charge pump and a loop filter are used for converting pulses output by a phase discriminator into a low-frequency direct-current control level, and controlling the delay amount of a delay chain to adjust a phase difference between the two clocks; when the two clocks are synchronized, the phase discriminator outputs a locking signal; a variable delay line is constructed by serial connection of a plurality of same sub-delay units in order to obtain a multi-phase clock; and the clock offset error calibration module is used for reducing a clock offset error by adopting a multi-phase clock circuit matching calibration technology. The clock signal can meet strict requirements on clock signals in high-frequency applications.

Description

technical field [0001] The invention relates to a low-jitter multi-phase clock circuit, in particular to an ultra-high-speed low-jitter multi-phase clock circuit for multi-channel time-interleaving analog-to-digital converters, and belongs to the field of integrated circuit clock systems. Background technique [0002] The bandwidth that each semiconductor process can provide is always limited, so the conversion rate of the corresponding analog-to-digital converter is also limited. In order to further increase the conversion rate of the analog-to-digital converter, a time-interleaved operation mode of multiple analog-to-digital converters can be adopted, that is, a time-interleaved analog-to-digital converter (TI ADC: Time Interleaved ADC). Time-interleaved ADC can achieve faster conversion rate with slower technology, so it has always been a research hotspot. This method was proposed by Black and Hodges in 1980, and has been widely studied and applied later. Foreign resear...

AI Technical Summary

Problems solved by technology

Phase jitter will increase the noise floor of the ADC and reduce its signal-to-noise ratio (SNR), while clock skew will increase the spurs of the ADC, affecting the signal-to-noise ratio and spurious-free dynamic range (SFDR) of the ADC

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