47results about How to "Increase bit density" patented technology

Roughly described, a memory device has a multilevel stack of conductive layers. Pillars oriented orthogonally to the substrate each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines (SSLs) are disposed above the conductive layers, and bit lines are disposed above the SSLs. The pillars are arranged on a regular grid having a unit cell which is a non-rectangular parallelogram. The pillars may be arranged so as to define a number of parallel pillar lines, each having an acute angle θ>° relative to the bit line conductors, each line of pillars having n>1 pillars intersecting a common one of the SSL. The arrangement permits higher bit line density, a higher data rate due to increased parallelism, and a smaller number of SSLs, thereby reducing disturbance, reducing power consumption and reducing unit cell capacitance.

Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle θ where tan(θ)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

The present invention allows video images with improved subjective quality to be transmitted without a concomitant increase in a total number of bits transmitted per frame. Quantization parameters are applied to coefficients of macroblocks within a given video frame. A lower value of quantization parameter is applied near a central region of a video frame. This central region is referred to as a prime video region. Applying a lower quantization parameter to the prime video region has the effect of increasing the bit density within that area thereby improving the video quality. Outside of the prime video region, the bit density is progressively decreased on a macroblock-by-macroblock basis so as to have a zero or near-zero net-gain in bit density over the entire video frame.

The present invention allows higher quality video images to be transmitted without a concomitant increase in a total number of video data bits transmitted per frame. Quantization parameters are applied to coefficients of macroblocks within a given video frame. A lower value of the quantization parameter is applied near a central region of a video frame. This central region is referred to as a prime video region. Applying the lower quantization parameter to the prime video region has the effect of increasing the video data bit density within that area. Outside of the prime video region, the video data bit density per macroblock is decreased so as to have a zero net-gain in bit density over the entire video frame. Furthermore, there may be a plurality of prime video regions where quantization parameters are dynamically coded. In this case, the value of the quantization parameter will increase or decrease within a given prime video region based on a relative importance of a particular prime video region. Consequently, a quantization parameter matrix may vary depending on the video scene.

The invention discloses a memory cell of a flash memory and a forming method. The memory cell of the flash memory comprises a semiconductor substrate, an isolating layer, a base layer selecting grid, a base layer dielectric layer, control grid layers, a memory plugging array and a plurality of polycrystalline silicon layers. The semiconductor substrate comprises an array area and step areas and the step areas are arranged at two sides of the array area. The isolating layer, the base layer selecting grid and the base layer dielectric layer are sequentially arranged on the surface of the semiconductor substrate. The control grid layers are arranged on the surface of the base layer dielectric layer. The control grid layers further comprises a plurality of polycrystalline silicon layers and a plurality of interlayer dielectric layers arranged on the surfaces of the polycrystalline silicon layers. The memory plugging array penetrates through the control grid layers of the array area in a thickness direction. The polycrystalline silicon layers are arranged in the control grid layers of the step areas and form a ladder layer by layer from the lowermost layer to the topmost layer in a decreasing mode. Projections of steps of all levels of the ladder on the semiconductor substrate are arranged in the shape of a line, and the line is parallel to the boundaries of the array area and the step areas. According to the memory cell of the flash memory, bit density of the flash memory is improved, and cost is reduced.

The invention relates to a medical system comprising a detection device for detecting an object in at least two dimensions by x-rays. The detection device is constructed to detect the object and to produce data comprising a 2D data record or a sequence of 2D data records over time representing the object in a projection through the object in two dimensions and to output the data. The medical system comprises at least one storage device with a data input actively connected to the detection device and which is constructed to receive the data at the input side and to write on a storage medium, in particular a portable storage medium, in such a way that the storage medium represents the data so it can be read out again. The medical system is constructed to digitally transmit the data from the detection device through to the storage device.

A ternary logic circuit according to the present invention includes a pull-up device (100) and a pull-down device (200) connected in series between power voltage sources (V_DD and GND), and an input voltage (V_IN) source and output voltage (V_OUT) source. When both the pull-up device (100) and the pull-down device (200) are turned off by an input voltage (V_IN), both the pull-up device (100) and the pull-down device (200) operate as simple resistors which are affected only by an output voltage (V_OUT) and form a ternary digit (“1” state) through voltage division. When only one of the pull-up device (100) or the pull-down device (200) is turned on to allow a current to flow therethrough, V_DD (“2” state) or GND (“0” state) is output as the output voltage (V_OUT). Accordingly, a bit density can be remarkably increased.

The embodiment of the invention provides a manufacturing method of a three-dimensional memory. The manufacturing method comprises the following steps forming a three-dimensional memory with four layers of stacked memory unit modules, wherein the manufacturing method of each layer of memory unit module comprises the following steps forming a first address line material layer, forming a plurality ofmemory units on the first address line material layer, and forming a second address line material layer above the plurality of memory units, wherein the projection of the address line of the first address line material layer on a first plane is perpendicular to the projection of the address line of the second address line material layer on the first plane, the projections of the address lines ofthe first address line material layers in different memory unit modules on the first plane are partially overlapped, and the projections of the address lines of the second address line material layersin different memory unit modules on the first plane are partially overlapped.

The present invention provides a method and device for fabricating high density memory device. Similar to a Hard Disk Drive (HDD), the integrated memory device is consisted with a rotating media plate and a Read/Write (R/W) head on a movable suspension. Unlike HDD where the media plate is coupled to a motor, the media plate is micro fabricated on a semiconductor substrate and is also a motor which is actuated and rotated by electrostatic forces. The head suspension is also micro fabricated and anchored to an electrostatic comb drive micro actuator. Control IC can also be integrated on-chip with the integrated memory device as well as acceleration sensing devices such as MEMS accelerator for anti-shock measures. The integrated disk storage device is fabricated by conventional semiconductor and MEMS fabrication process technology.

The optical recording material of the invention is an optical recording material used for an optical recording medium capable of recording information by irradiation of light, the optical recording medium being an optical recording medium which records information at a linear speed of at least 14 m/sec, wherein the dye component in the optical recording material comprises at least one type of chelate compound of an azo compound and a metal, and when the dye component is used as a sample for thermogravimetry in an inert gas atmosphere, the dye component sample exhibits a maximum weight reduction of 0.2-3.0%/° C. at 180-250° C.

The embodiment of the invention provides a three-dimensional memory with four stacked layers. The three-dimensional memory comprises at least one memory cell array block; wherein the memory cell arrayblock comprises a first bit line layer, a second bit line layer and a third bit line layer which are sequentially arranged from top to bottom and are parallel to one another, and the bit lines of thebit line layers are parallel to each other, and the projections of the bit lines of the bit line layers on the first plane are partially overlapped; a first word line layer between the first bit linelayer and the second bit line layer; a second word line layer between the second bit line layer and the third bit line layer; wherein the word lines of each word line layer are parallel to each other, and the projection of the word line of each word line layer on the first plane is vertical to the projection of the bit line of the first bit line layer on the first plane; and four memory cell layers which are respectively positioned between two adjacent bit line layers and word line layers.

The invention discloses a composite memory structure. The composite memory structure comprises a substrate, a flash memory, a first resistive random access memory and a second resistive random access memory, the flash memory is located on the substrate. The flash memory comprises a grid electrode, a first doped region and a second doped region. The gate is on the substrate. The first doped region is located in the substrate at one side of the gate. The second doped region is located in the substrate on the other side of the gate. The first resistive random access memory is electrically connected to one of the gate, the first doped region and the second doped region. The second resistive random access memory is electrically connected to the other one of the gate, the first doped region and the second doped region.