Semiconductor memory and method for manufacturing the same

Abstract

Provided are a semiconductor memory wherein bit density is improved by three-dimensionally arranging cells, and a method for manufacturing such semiconductor memory. In a semiconductor memory (1), a plurality of gate electrode films (21) are arranged on a silicon substrate (11). Gate electrode films (21) are arranged along one direction (X direction) parallel to the upper surface of the silicon substrate (11). Each gate electrode film (21) has a shape of a grid-like board, and a plurality of through holes (22) are formed in matrix when viewed from the X direction. Furthermore, a plurality of silicon beams (23) are arranged such that the beams penetrate the through holes (22) on the gate electrode films (21) and extend in the X direction. Furthermore, an ONO film (24), including a charge accumulating layer, is arranged between the gate electrode film (21) and the silicon beam (23).

Description

technical field [0001] The present invention relates to a semiconductor memory and a method of manufacturing the same, and more particularly, to a semiconductor memory including three-dimensionally arranged memory cells and a method of manufacturing the same. Background technique [0002] Flash memory is widely used as high-capacity data storage in cellular phones, digital cameras, USB (Universal Serial Bus) memory, silicon audio players, etc. The cost is reduced and the market continues to expand. In addition, new applications are rapidly emerging, enabling a virtuous cycle in which scaling down and lower manufacturing costs find new markets. [0003] In particular, NAND flash memory allows a plurality of active areas (hereinafter also referred to as "AA") to share a gate conductor (hereinafter also referred to as "GC"), thereby substantially realizing a 4F 2 The intersection primitive with a primitive area of ​​, where F is the minimum processing size, is being rapidly s...

AI Technical Summary

Problems solved by technology

[0006] (2) The short-channel effect and the narrow-channel effect become prominent rapidly due to the device size reduction accompanying the scaling down, which makes it difficult to ensure the reliability and fast operation of the nonvolatile memory generation by generation

Therefore, an increase in the number of memory layers leads to an increase in the number of manufacturing steps, and also leads to an increase in manufacturing cost

As a result, this technology has the problem of manufacturing cost per bit

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