Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions

Abstract

An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels / yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to 15 each of the circuit parameters are determined. The memory cell design parameters and / or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and / or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield. Multiple cell designs can be compared for performance, yield and sensitivity of performance variables to circuit parameters over particular environmental conditions in order to select the best cell design.

Description

BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The present invention relates generally to memory circuit design methodologies and programs for designing digital memory circuits, and more particularly to a method and computer program for improving static memory performance across process variations and environmental conditions. [0003] 2. Description of the Related Art [0004] Memory speed and other performance factors are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memories (SRAMS) and memory cells are used in processor caches, registers and in some designs external to the system processors for fast access to data and program instructions. [0005] With processor cycle frequencies reaching well above 4 Ghz, development of SRAM cells that can store and provide access to stored values within that period has become necessary. However, at proc...

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Benefits of technology

[0012] One aspect of the invention represents an improvement over traditional memory cell modeling, as multiple statistical analyses are performed on only a subset of circuit parameters for each of several performance variables, while other parameters are fixed. The subset of circuit parameters are also varied systematically over the multiple analyses so that sensitivities can be determined. The results of the statistical analyses are used to compute sensitivities of the performance variables to the cell parameters and the cell parameters and / or operating conditions are adjusted in conformity with the sensitivities in order to improve the memory cell design.

[0014] Because of the above-described technique, it is possible to extend the analysis beyond a traditional analysis that would extend to only 3σ (three standard deviations) to a level of 5σ and beyond for at least some of the parameters, increasing device yields. The increase in analysis speed (i.e., reduction in processing power requirements) makes it possible, for example, to extend an analysis to a level of 6σ or 7σ. Since the cells are not modeled over every device parameter, but only the parameters critical to the particular performance variable being modeled, computation time is reduced and sensitivities can be more effectively determined.

Problems solved by technology

Memory speed and other performance factors are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward.

However, at process scales necessary to achieve such access are also increasingly subject to variability in circuit parameters such as device threshold voltages and channel dimensions.

However, lower supply voltages typical dictate lower performance levels in terms of cell read and write stability and access delay.

Because of all of the above-described limitations, yield reduction due to SRAM cell variability or increased redundancy requirements will increase production cost and waste or limit available space and design flexibility in order to provide sufficient redundancy to maintain yields.

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