5 results about "Channel conductivity" patented technology

Modified fabrication processes for transistors with field plates, such as gallium nitride heterostructure transistors, reduce exposure of surfaces near the transistor channel, mitigating damage and performance degradation from sensitive surfaces and interfaces exposed to high temperatures and the risk of etch-induced damage. Such processes include sequential dielectric formation and patterning, allowing for gate electrode and field plate electrode formation after high temperature processing steps. A passivation layer can also serve as an etch stop for other dielectric materials, enabling protection of the channel region during dry etch processes followed by selective wet etching that removes the passivation layer immediately prior to gate electrode formation and other steps. Such methods also enable surface modification processes to be performed to selectively enhance channel conductivity, followed by passivation of the modified surface to maintain the enhanced conductivity during subsequent processing steps.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

Modified fabrication processes for transistors with field plates, such as gallium nitride heterostructure transistors, reduce exposure of surfaces near the transistor channel, mitigating damage and performance degradation from sensitive surfaces and interfaces exposed to high temperatures and the risk of etch-induced damage. Such processes include sequential dielectric formation and patterning, allowing for gate electrode and field plate electrode formation after high temperature processing steps. A passivation layer can also serve as an etch stop for other dielectric materials, enabling protection of the channel region during dry etch processes followed by selective wet etching that removes the passivation layer immediately prior to gate electrode formation and other steps. Such methods also enable surface modification processes to be performed to selectively enhance channel conductivity, followed by passivation of the modified surface to maintain the enhanced conductivity during subsequent processing steps.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

This invention discloses a radio frequency (RF) transistor based on a carbon nanotube array and its fabrication method. The RF transistor includes a substrate with an insulating surface, an active region formed by an oriented array of semiconductor-type carbon nanotubes, a gate dielectric layer, a gate metal layer, and source and drain electrodes. The active region is a channel functional region surrounded by a continuous carbon nanotube-free region, retaining only the carbon nanotube strips required for channel conductivity and the necessary source-drain contact overlap region; the carbon nanotube-free region has a clearance margin δ around the perimeter of the channel functional region. This method thoroughly removes all carbon nanotubes outside the active region through plasma etching, physically cutting off parasitic conduction paths and eliminating capacitive coupling effects. Compared to traditional local line isolation methods, this invention can improve transconductance by ≥35%, cutoff frequency by ≥20%, maximum oscillation frequency by ≥15%, and reduce gate-source parasitic capacitance by ≥25%, while significantly improving device consistency, making it suitable for large-scale RF array integration.