17 results about "Channel conductivity" patented technology

The invention belongs to the technical field of lead ion detection, and particularly relates to a black phosphorus field-effect tube lead ion detector and a use method thereof. The detector comprises an insulating substrate, a gate electrode layer, a gate electrode insulating layer, a sensitive layer, a source electrode and a drain electrode. The gate electrode layer is arranged on the insulating substrate, and the sensitive layer is arranged on the gate electrode insulating layer; particularly, the sensitive layer comprises a black phosphorus material, and noble metal particles are arranged on the surface of the sensitive layer. According to the invention, black phosphorus is used as a sensitive material of the field effect transistor, the black phosphorus and lead ions have good chemical matching property, and a stable coordination effect is formed through surface phosphorus atoms and lead ions, so that the conductivity of a channel is obviously changed; in addition, precious metal particles are introduced to the surface of the black phosphorus sensitive layer, so that the selective adsorption capacity of lead ions is enhanced. In a word, high-selectivity and high-sensitivity electrical detection of lead ions can be realized, and a high-performance field-effect tube sensor platform is provided for rapid monitoring of heavy metal pollutants.

To provide a driving method for a semiconductor device, in which the influence of variation in threshold voltage and variation in mobility of transistors can be reduced.SOLUTION: In a driving method for a semiconductor device including a transistor of an n-channel conductivity type, a switch for controlling the electric connection between a first terminal and a gate of the transistor, a capacitor element electrically connected between a second terminal and the gate of the transistor, and a display element, a first period for holding the sum of a video signal voltage and a voltage according to a threshold voltage of the transistor in the capacitor element, a second period for discharging, through the transistor, charges held in the capacitor element in accordance with the sum of the video signal voltage and the threshold voltage by making the switch conductive, and a third period for supplying current to the display element through the transistor after the second period are provided.SELECTED DRAWING: Figure 1

This invention discloses a two-dimensional gallium oxide ferroelectric gate enhancement-mode field-effect transistor and its fabrication method, belonging to the field of semiconductor device technology, and solving the problem of the difficulty in fabricating enhancement-mode Ga2O3 devices. The transistor includes a substrate layer, a channel layer, and an electrode layer connected layer by layer. The channel is obtained by mechanically lifting or epitaxially fabricating a Ga2O3 thin film, which is simpler and easier to operate compared to other fabrication methods. In addition, the substrate can be selected from a wide range of materials with good compatibility. The structure of the charge storage gate has minimal impact on the channel conductivity. The two-dimensional ferroelectric gate acts as a charge storage gate, utilizing its spontaneous in-plane and out-of-plane polarization effects to collect channel carriers and deplete the channel, thus realizing an enhancement-mode Ga2O3 device.

This semiconductor integrated circuit includes: a first insulated gate field effect transistor having a first floating gate electrode in an electrically floating state, and having a first channel conductivity type; a second insulated gate field effect transistor having a second floating gate electrode formed integrally with the first floating gate electrode and being in an electrically floating state, and having a second channel conductivity type opposite to the first channel conductivity type; and a first capacitive element electrically coupled in series to the first floating gate electrode and the second floating gate electrode, and including a ferroelectric insulator.

The invention belongs to the field of organic electrochemical transistors, and particularly discloses a preparation method and application of an integrated thermoelectric grid-control organic electrochemical transistor. The integrated thermoelectric grid-control organic electrochemical transistor sequentially comprises a substrate layer, an electrode layer (comprising a source electrode and a drain electrode), a channel layer, an insulating layer, a thermoelectric module and a dielectric layer from bottom to top, and the thermoelectric module is made of an ion thermoelectric gel material with a Sore effect. No-grid-voltage driving is realized by using the Sore effect of ion thermoelectric gel: when a temperature gradient exists at two ends of the thermoelectric module, internal movable ions are directionally migrated due to thermal diffusion, an ion concentration difference is formed, stable thermoelectric potential is generated, and the potential acts on a channel layer as a grid regulation and control signal to regulate and control the conductivity of a channel. Dependence of a traditional electrical regulation transistor on grid voltage is eliminated, the transistor has the advantages of being simple in structure, low in power consumption and the like, and a brand new strategy is provided for functionalization and intellectualization of the transistor and an integrated circuit.

The invention relates to a soluble covalent organic framework (COF) and application thereof in a lithium metal battery. The covalent organic framework is formed by condensing aromatic amine with a methyl polyethylene glycol (mPEG) side chain and an aromatic aldehyde monomer, and has high crystallinity, redox activity and ion channel conductivity. The COF can be used as an artificial solid electrolyte interface layer (ASEI) to be coated on the surface of a lithium metal negative electrode, so that the interface stability is improved, and the growth of lithium dendrites is inhibited. Experiments show that the material shows excellent cycling stability and capacity retention ratio in an ester electrolyte, and is suitable for a new generation of high-performance rechargeable lithium metal batteries.

Modified fabrication processes for transistors with field plates, such as gallium nitride heterostructure transistors, reduce exposure of surfaces near the transistor channel, mitigating damage and performance degradation from sensitive surfaces and interfaces exposed to high temperatures and the risk of etch-induced damage. Such processes include sequential dielectric formation and patterning, allowing for gate electrode and field plate electrode formation after high temperature processing steps. A passivation layer can also serve as an etch stop for other dielectric materials, enabling protection of the channel region during dry etch processes followed by selective wet etching that removes the passivation layer immediately prior to gate electrode formation and other steps. Such methods also enable surface modification processes to be performed to selectively enhance channel conductivity, followed by passivation of the modified surface to maintain the enhanced conductivity during subsequent processing steps.

Methods, systems, and devices for dynamic select gate scan management are described. For example, a memory system may perform a first evaluation of selection transistors (e.g., string selection transistors in a 3D NAND array), determine a result of operating the selection transistors based on performing the first evaluation, and perform a second evaluation of the selection transistors based on an access interval that is determined as a function of the result associated with the first evaluation. The result of the evaluation may indicate a quantity of selection transistors with a channel conductivity above a threshold conductivity when applying a voltage to gates of the selection transistors, and larger results (e.g., larger quantities of failed selection transistors) may be mapped to shorter access intervals (e.g., in accordance with an inverse relationship, to increase evaluation frequency as a quantity of degraded selection transistors increases).

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

Modified fabrication processes for transistors with field plates, such as gallium nitride heterostructure transistors, reduce exposure of surfaces near the transistor channel, mitigating damage and performance degradation from sensitive surfaces and interfaces exposed to high temperatures and the risk of etch-induced damage. Such processes include sequential dielectric formation and patterning, allowing for gate electrode and field plate electrode formation after high temperature processing steps. A passivation layer can also serve as an etch stop for other dielectric materials, enabling protection of the channel region during dry etch processes followed by selective wet etching that removes the passivation layer immediately prior to gate electrode formation and other steps. Such methods also enable surface modification processes to be performed to selectively enhance channel conductivity, followed by passivation of the modified surface to maintain the enhanced conductivity during subsequent processing steps.

The invention discloses an oxide thin film transistor array preparation and physiological electric signal monitoring method based on hydrophilic and hydrophobic patterning, and belongs to the field of semiconductor materials and devices and biosensing. Forming a pattern with a hydrophilic region and a hydrophobic region on the surface of the substrate; the surface energy difference between the hydrophilic region and the hydrophobic region is utilized, an oxide semiconductor precursor solution is spin-coated, so that the precursor solution selectively infiltrates the hydrophilic region, and a patterned oxide semiconductor film is obtained through pre-annealing and annealing treatment; depositing a metal electrode on the patterned oxide semiconductor thin film by adopting a vacuum evaporation method to form a thin film transistor array; the thin film transistor array is used as a pre-amplifier, and the channel conductivity is modulated in real time by connecting the potential difference of the physiological electric signals to the grid electrodes of the transistors in series, so that the synchronous monitoring of the multi-channel physiological electric signals is realized.

The application provides a kind of space closed type magnetohydrodynamic power generation system cesium additive concentration on-line monitoring method and device, and the working medium of closed type magnetohydrodynamic circulation system is the helium-cesium binary mixed working medium formed by helium and cesium vapor, wherein the cesium vapor is the additive for enhancing electrical conductivity, and the cesium vapor concentration directly determines the channel conductivity and power generation performance. By using the physical characteristics that the constant volume specific heat capacity of helium and cesium vapor differs by about 31 times, a micro calorimetric sensing unit is connected in parallel on the closed loop magnetohydrodynamic circulation system, the cesium concentration is inverted by micro sampling, constant power heating and accurate measurement of temperature rise rate, which provides the basis for electrical conductivity prediction and adaptive control. Innovatively, the temperature rise rate and steady-state temperature difference are used to invert the double parameters, the total mass of the sensing unit is ≤50g, the power consumption is ≤2W, and the volume is ≤20cm³.

The application discloses a multi-path conductivity measuring device and a water treatment equipment, wherein the multi-path conductivity measuring device comprises an electric control board, multi-path TDS detection probes and a main control circuit. The main control circuit is arranged on the electric control board, and the main control circuit is connected with the multi-path TDS detection probes. The application is characterized in that each TDS detection probe is arranged in the corresponding water solution to be measured to collect the conductivity of the water solution to be measured and output a TDS detection signal, and then the main control circuit is used to determine the water quality layer of the water solution, so that the application is rapidly applied to a multi-stage water treatment equipment, the cost is reduced, and the practicability is improved.

Apparatus and techniques for reducing read interference in a memory device by reducing channel gradient and charge injection to memory cells are described. Before reading a memory cell in a selected NAND string, the channel of an unselected NAND string is boosted. This boosting involves simultaneously increasing the voltage signal of a non-adjacent word line of the selected word line WLn to the read pass voltage while selecting the gate transistor on the drain side to turn it on and off, and increasing the voltage signal of the non-adjacent word line of the selected word line WLn to the read pass voltage, while applying a positive voltage to the source and drain terminals of the unselected NAND string. The voltage signal of the adjacent word lines of WLn: increases to a peak level to enhance channel conductivity for faster reading, wherein the peak level is less than the read pass voltage; decreases to a lower level to reduce the channel gradient and thus reduce read interference; and then increases to the read pass voltage.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

Disclosed is a drive backplane relating to the technical field of display. The drive backplane comprises a base substrate, and a first active layer, a first gate electrode, a first interlayer dielectric layer, a first source / drain electrode, a first passivation layer, and a second passivation layer that are arranged in a direction away from the base substrate. The orthographic projection of the first active layer on the base substrate at least partially overlaps with the orthographic projection of the first interlayer dielectric layer on the base substrate. The manufacturing material of the first interlayer dielectric layer comprises an oxide. The hydrogen content of the first passivation layer is less than the hydrogen content of the second passivation layer. The present application can improve the problem of channel conductivity caused by diffusion of hydrogen atoms to the first active layer.

This invention discloses a radio frequency (RF) transistor based on a carbon nanotube array and its fabrication method. The RF transistor includes a substrate with an insulating surface, an active region formed by an oriented array of semiconductor-type carbon nanotubes, a gate dielectric layer, a gate metal layer, and source and drain electrodes. The active region is a channel functional region surrounded by a continuous carbon nanotube-free region, retaining only the carbon nanotube strips required for channel conductivity and the necessary source-drain contact overlap region; the carbon nanotube-free region has a clearance margin δ around the perimeter of the channel functional region. This method thoroughly removes all carbon nanotubes outside the active region through plasma etching, physically cutting off parasitic conduction paths and eliminating capacitive coupling effects. Compared to traditional local line isolation methods, this invention can improve transconductance by ≥35%, cutoff frequency by ≥20%, maximum oscillation frequency by ≥15%, and reduce gate-source parasitic capacitance by ≥25%, while significantly improving device consistency, making it suitable for large-scale RF array integration.