77results about How to "High equipment integration" patented technology

There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.

An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

The invention relates to a dynamic performance testing system for a fuel cell automobile power system. The dynamic performance testing system comprises an environment simulation module, a noise vibration and harshness (NVH) test matching module, an engine hardware-in-loop test matching module for testing, an electric driving system hardware-in-loop test matching module for testing, an automobile power system hardware-in-loop test matching module for testing, an analogue simulation module, a power load parameter observe and control module and a master control management module. The environment simulation module and the NVH test matching module are used for providing actual working conditions. The analogue simulation module is used for simulating operation environment parameters of the actual working conditions under the software environment. The power load parameter observe and control module is used for testing and controlling the power parameters of the engine hardware-in-loop test matching module and load parameters of the electric driving system hardware-in-loop test matching module. The master control management module is connected with the other modules and used for controlling and saving the testing data in real time. Compared with the prior art, the dynamic performance testing system is high in integrity and good in generality, can simulate the actual working conditions, and can comprehensively take the influence of the hot environment and the vibration noise environment on the fuel cell automobile power system into account.

The present invention relates to a method and device for fabricating an integrated flywheel device using semiconductor materials and IC/MEMS processes. Single crystal silicon has high energy storage/weight ratio and no defects. Single crystal silicon flywheel can operate at much higher speed than conventional flywheel. The integrated silicon flywheel is operated by electrostatic motor and supported by electrostatic bearings, which consume much less power than magnetic actuation in conventional flywheel energy storage systems. The silicon flywheel device is fabricated by IC and MEMS processes to achieve high device integration and low manufacturing cost. For the integrated silicon flywheel, high vacuum can be achieved using hermetic bonding methods such as eutectic, fusion, glass frit, SOG, anodic, covalent, etc. To achieve larger energy capacity, an array of silicon flywheels is fabricated on one substrate. Multiple layers of flywheel energy storage devices are stacked.

A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens including a first insulating layer having an uneven surface and a second insulating layer covering upper and side surfaces of a projected portion of the first insulating layer to form a dome shape, and a planarization layer formed on the micro-lens, and a color filter formed on the planarization layer.

An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

The invention discloses a sewage treatment device, comprising a fan, a water pump and a tank body. The upper part of the tank body is provided with a sewage inlet and an exhaust port; a Z shape separator is fixed inside the tank below the sewage inlet; the Z shape separator comprises an upper baffle plate, a vertical baffle plate, a lower baffle plate, and divides the tank body into four regions; the upper baffle plate is provided with a plurality of reflux holes, the reflux holes are equipped with anti-reflux nozzles for preventing the water above the upper baffle plate from flowing to the lower position; a membrane module is fixed below the upper baffle plate, and a hanging membrane packing assembly is fixed above the lower baffle plate; a left aeration device is fixed below the membrane assembly, and is connected with a fan outside the tank body through a gas supply pipeline; a water inlet of the water pump outside the tank body is connected with a membrane assembly water outlet duct through a water pipes; and the gas supply pipeline and the water pipe are equipped with installation valves. The device integrates two sewage treatment technology and equipment of biological membrane method and a membrane bioreactor, and has the advantages of small land occupation, and low investment and operating cost.

A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material.

A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.

A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word lines, and a second select gate line are corresponding to a memory cell row. The intersections of the dummy bit line with the first select gate line, the word lines, and the second select gate line are corresponding to a dummy memory cell row. A source line is disposed on the substrate at one side of the memory cell rows, wherein the dummy memory cell row and the dummy bit line are served as a current path for connecting the source line.

A magnetic random access memory (MRAM) using a schottky diode is disclosed. In order to achieve high integration of the memory device, a word line is formed on a semiconductor substrate without using a connection layer and a stacked structure including an MTJ cell, a semiconductor layer and a bit line is formed on the word line, thereby forming the schottky diode between the MTJ cell and the bit line. As a result, a structure of the device is simplified, and the device may be highly integrated due to repeated stacking.

A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

A method of fabricating a T-shaped polysilicon gate by using dual damascene process. An oxide layer, a hard mask layer, and a patterned first photoresist layer in sequence are formed on a semiconductor substrate. Using the patterned first photoresist layer as a mask, an etching process is performed on the hard mask layer to form a first trench. The patterned first photoresist layer is removed. An organic layer is then deposited in the first trench. A patterned second photresist layer is formed on the semiconductor substrate. Using the patterned second photresist layer as a mask, an etching process is performed on the hard mask layer to define a second trench dimension. The patterned second photoresist layer and the organic layer are removed. An oxide layer and a polysilicon layer are deposited in the first trench and the second trench. The residual hark mask layer is removed to obtain a T-shaped profile polysilicon gate.

The invention belongs to the technical field of nuclear power automation tests, and relates to a DCS automation test device based on a virtual instrument. The device comprises a computer module as a control device and a virtual instrument module as an execution device of the test, the virtual instrument module comprises a data acquisition/output module and a communication module, the data acquisition/output module processes three kinds of signals including signals output to the test device by a DCS, signals output to the DCS by the test device, and DCS two-layer display image grayscale acquisition/screen touch signals, and the communication module comprises a network communication unit and an industrial field bus communication unit. According to the device, the one-layer logic function andthe two-layer display function of the DCS system and the communication function between DCS devices can be tested, and defects of insufficient test tool resources and single function of the conventional nuclear power station DCS are overcome.