30results about How to "Low leakage current" patented technology

A solid electrolytic capacitor that comprises an anode that contains a valve-action metal (e.g., tantalum, niobium, and the like) and a dielectric film overlying the anode is provided. The capacitor also comprises a protective coating overlying the dielectric film, wherein the protective coating contains a relatively insulative, resinous material. For example, in one embodiment, the resinous material can be a drying oil, such as olive oil, linseed oil, tung oil, castor oil, soybean oil, shellac, and derivatives thereof. The capacitor also comprises a conductive polymer coating overlying the protective coating. As a result of the present invention, it has been discovered that a capacitor can be formed that can have a relatively low leakage current, dissipation factor, and equivalents series resistance.

A cross-point RRAM memory array includes a word line array having an array of substantially parallel word lines therein and a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed between said word lines and said bit lines. A memory resistor located between said word lines and said bit lines at each cross-point. A high-open-circuit-voltage gain, bit line sensing differential amplifier circuit located on each bit line, including a feedback resistor and a high-open-circuit-voltage gain amplifier, arranged in parallel, wherein a resistance of the feedback resistors is greater than a resistance of any of the memory resistors programmed at a low resistance state.

A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.

An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

The invention relates to an overvoltage protection device and to a method for fabricating such a device. A substrate (1) is provided with a first electrode layer (2), above which extends a second electrode layer (3) which is separated from the first electrode layer (2) by a distance (d) determined by the thickness of a spacing layer (4). The spacing layer (4) has an opening (5) which forms a cavity (6) between the electrode layers (2, 3).

The invention relates generally to a nanolaminate structure involving Al₂O₃ thin films as a main component. The nanolaminate is used between a top electrode and a bottom electode to form a capacitor. The naonolaminate layer comprises alternating layers of Al₂O₃ and TiO₂ and an interfacial layer.

The invention provides a surface mounting type overvoltage and overcurrent protection device and a manufacturing method thereof. The surface mounting type overvoltage and overcurrent protection device comprises a protection device body, wherein the left end and the right end of the protection device body are provided with end electrodes; the front side and the rear side of the protection device body are provided with side electrodes; at least one melt layer electrode, at least two first electrode layers and at least two second electrode layers are arranged inside the protection device body; the melt layer electrode is covered by an arc extinction material coating; through holes are formed between the first electrode layers and the second electrode layers; piezoresistor function phases are filled in the through holes. The surface mounting type overvoltage and overcurrent protection device is manufactured by the steps of molding LTCC (Low Temperature Co-Fired Ceramic) membranes, printing the melt layer electrode, printing electrode layer electrodes, printing the arc extinction material coating, forming the through holes in the LTCC stacked membranes, filling the piezoresistor function phases in the through holes, stacking according to the design, cutting to form a single product, sintering the product, forming the end electrodes and the side electrodes and the like. The surface mounting type overvoltage and overcurrent protection device has the advantages of low electric capacity, low leakage conductance current, rapid response speed, and high reliability and stability.

A transistor with stable electrical characteristics or a transistor with normally-off electrical characteristics. The transistor is a semiconductor device including a conductor, a semiconductor, a first insulator, and a second insulator. The semiconductor is over the first insulator. The conductor is over the semiconductor. The second insulator is between the conductor and the semiconductor. The first insulator includes fluorine and hydrogen. The fluorine concentration of the first insulator is higher than the hydrogen concentration of the first insulator.

A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface.

The invention relates to a B-site Mn and Cu codoped high remanent polarization BiFeO3 film and a preparation method, the method comprises the following steps: dissolving bismuth nitrate, ferric nitrate, manganese acetate and cupric nitrate according to mol ratio of 1.05: [(0.92-0.98)-x]: (0.02-0.08):x in a mixed liquor of ethylene glycol monomethyl ether and acetic anhydride, then uniformly stirring to obtain a BiFeO3 precursor; wherein total metal ion concentration of the BiFeO3 precursor is 0.1-0.5mol/L, X is 0.01-0.03; performing spin coating of the BiFeO3 precursor on a FTO/glass substrate to prepare a wet membrane, baking the wet membrane to obtain a dry membrane, then annealing at 550 DEG C to obtain the crystalline state BiFeO3 film; cooling the crystalline state BiFeO3 film, and repeatedly making the crystalline state BiFeO3 film to reach a required thickness to obtain the B-site Mn and Cu codoped high remanent polarization BiFeO3 film. According to the invention, a sol gel technology is employed, the equipment requirement is simple, the film is prepared on large surface and surfaces with irregular shapes, the chemical component is accurate and controllable, and the regulation and control to its crystal structure can be carried out by codoping thereby the ferroelectric performance of the film is greatly increased.

An electrode for an electrochemical device, including an elongated collector, a lead provided halfway along a longitudinal direction of the collector, and active material layers provided on the collector, wherein when L_a (m) is a distance from one end of the collector, in the longitudinal direction, up to the lead, and L_b (m) is a distance from the other end of the collector, in the longitudinal direction, up to the lead, and ρ (Ωm) is a resistivity of the collector at 25°, where L_opt (m) being 1.9×10⁶ρ, the L_a (m) and L_b (m) are from 0.95 L_opt to 1.05 L_opt respectively.

A method of making a bi-directional transient voltage suppression device is provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.

The invention is a novel class of materials made by combining the best qualities of both lead iron tantalate (PFT) and lead iron titanate (PZT) to synthesize (PbZr_0.53Ti_0.47O₃)_(1-x)—(PbFe_0.5Ta_0.5O₃)_x (PZTFT) (0.1≦x≦0.9) compositions that have multiferroic (ferroelectric and ferromagnetic) and magnetoelectric properties.

A semiconductor device includes a first electrode, a second electrode, and a multi-layer stack positioned between the first electrode and the second electrode, the multi-layer stack including at least one anti-ferroelectric layer and at least one high-k dielectric layer.

A technique capable of forming a side wall of a gate electrode having high resistance-to-etching and low leakage current is provided. A method of manufacturing a semiconductor device according to the technique includes: (a) loading a substrate into a processing space in a process vessel, the substrate having thereon a gate electrode and an insulating film formed on a side surface of the gate electrode as a side wall; and (b) forming an etching-resistant film containing carbon and nitrogen on a surface of the insulating film by supplying a carbon-containing gas into the processing space.

The invention discloses a low-voltage TVS device with an ultralow electric leakage level and a manufacturing method thereof. The N+ breakdown region (1) and the N+ gettering region (2) of the longitudinal structure can use a vertical crossed structure or a circular annluar structure. The N+ gettering region (1) has a junction depth of 15 to 25 [mu]m and a width range of 20 to 50 [mu]m. The N+ breakdown region (2) has a junction depth of 8 to 15 [mu]m and a width range customized according to different IPP requirements. The N+ gettering region and the N+ breakdown region have gap design requirements of 5 to 50 [mu]m. The main purpose of the N+ gettering region is to absorb oxidation-induced defects generated in the high temperature process of silicon single crystal, and generate a severe defect region. The N + breakdown region is actually the effective working region of the device. The low-voltage TVS device achieves alow electric leakage level and satisfies a requirement for a high IPP current-through capability.

A mesa-type bidirectional Shockley diode including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of said regions of the first conductivity type, each buried region being complementary in projection with the other; and a groove arranged in the vicinity of the periphery of the component on each of its surfaces, the component portion external to the groove comprising, under the external portion of the upper and lower regions of the second conductivity type, regions of the first conductivity type of same doping profile as said buried regions.

The capacitor material of the present invention is comprised by laminating a titanium dioxide layer and a titanate compound layer having perovskite crystals.

The present invention relates to a non-fullerene acceptor compound containing benzoselenadiazole, and organic optoelectronic devices comprising the same.

Disclosed are a storage device, a manufacturing method thereof, and electronic equipment including the storage device. According to an embodiment, a memory device may include a plurality of memory cell layers sequentially stacked on a substrate, each memory cell layer includes an array of memory cells, and the memory cells in each memory cell layer are along the stacking direction of the memory cell layers are substantially aligned with each other. Each memory cell includes: a first source/drain layer, a channel layer, and a second source/drain layer stacked in sequence, wherein the channel layer includes a semiconductor material different from that of the first and second source/drain layers; and A memory gate stack is formed around the periphery of the channel layer. The memory gates of the memory cells in the same memory cell layer are stacked into one body. For each storage unit, its first source/drain layer is integrated with the second source/drain layer of the corresponding storage unit in the lower layer, and its second source/drain layer is integrated with the first source/drain layer of the corresponding storage unit in the upper layer.