30results about How to "Low leakage current" patented technology

The invention discloses a memory device, a manufacturing method thereof and an electronic device comprising the memory device. According to an embodiment, the memory device may include a plurality offirst columnar active regions, a plurality of second columnar active regions, a plurality of layers of first memory gate stacks and a plurality of layers of second memory gate stacks; the first columnar active regions and the plurality of second columnar active regions are formed on a substrate and extend upwardly; the first columnar active regions and the plurality of second columnar active regions are respectively arranged as a first array and a second array; each first columnar active region includes source / drain layers and channel layers which are alternately stacked; corresponding channellayers in the first columnar active regions are substantially coplanar; corresponding source / drain layers in the first columnar active regions are substantially coplanar; each second columnar activeregion includes an integrally-extending active semiconductor layer; the plurality of layers of first memory gate stacks are substantially coplanar with the channel layers; the plurality of layers of first memory gate stacks surround the peripheries of the channel layers on corresponding planes respectively; and the plurality of layers of second memory gate stacks surround the peripheries of the second columnar active regions respectively.

Disclosed are a storage device, a manufacturing method thereof, and electronic equipment including the storage device. According to an embodiment, a memory device may include a plurality of memory cell layers sequentially stacked on a substrate, each memory cell layer including a first array of first memory cells and a second array of second memory cells, the first array and The second arrays are nested within each other. The first and second memory cells in each memory cell layer are substantially substantially to each other along the stacking direction of the memory cell layers. Each first memory cell is a vertical device based on sequentially stacked first source / drain layers, channel layers and second source / drain layers. Each second memory cell is a vertical device based on an active semiconductor layer extending in the stacking direction. Each of the first memory cells and each of the second memory cells includes respective memory gate stacks, and they share a gate conductor layer. The gate conductor layers in the same memory cell layer are integrated.

Disclosed are a storage device, a manufacturing method thereof, and electronic equipment including the storage device. According to an embodiment, a memory device may include: a plurality of first columnar active regions formed on a substrate and extending upward from the substrate, wherein each first columnar active region has a circular cross-section; a first storage gate formed on the inner sidewall of each first columnar active region; and a multilayer control gate formed around the outer sidewall of each first columnar active region.

The invention provides a surface-mounted overvoltage and overcurrent protection device and a manufacturing method thereof, comprising a protection device body, end electrodes are provided at the left and right ends of the protection device body, and side electrodes are provided at the front and rear sides to protect the device body. The device body is provided with at least one melt layer electrode, at least two first electrode layers, and at least two second electrode layers, and the melt layer electrode is covered by an arc-extinguishing material coating, the first electrode layer and the second electrode layer There are through holes between the electrode layers and they are filled with piezoresistive functional phases. Forming through LTCC ceramic diaphragm --> melt layer electrode printing --> electrode layer electrode printing --> arc extinguishing material coating printing --> forming a through hole in the LTCC ceramic stack diaphragm --> filling pressure in the through hole Functional phase of the sensitive resistor --> stacked according to the design --> cut into a single product --> product sintering --> forming end electrodes and side electrodes and other steps. It has the advantages of low capacitance, low leakage current, fast response, high reliability and stability.

Disclosed are a storage device, a manufacturing method thereof, and electronic equipment including the storage device. The storage device may include: a plurality of first columnar active regions and a plurality of second columnar active regions extending upward on the substrate, arranged in first and second arrays respectively, and each first columnar active region includes a source / Drain layers and channel layers are alternately stacked, the corresponding channel layers in each first columnar active region are on substantially the same plane, and the corresponding source / drain layers are on substantially the same plane, and each second The columnar active region includes an integrally extended active semiconductor layer; a columnar conductive contact part located at the lower part of each second columnar active region; an insulating layer formed around the periphery of each columnar conductive contact part; Multi-layer first storage gate stacks in substantially the same plane and respectively surrounding the periphery of each channel layer on the corresponding plane; multi-layer second storage gate stacks surrounding the periphery of each second columnar active region.

Disclosed are a storage device, a manufacturing method thereof, and electronic equipment including the storage device. According to an embodiment, the memory device may include a memory cell and a selection device sequentially stacked on a substrate. Each of the memory unit and the selection device may include: a first source / drain layer, a channel layer, and a second source / drain layer stacked in sequence, wherein the channel layer includes a layer different from the first and second source / drain layers a semiconductor material; and a gate stack formed around the periphery of the channel layer. The gate stack of the memory cell is a memory gate stack.

The invention provides a method for preparing a bismuth ferrite film with dielectric property by adopting a liquid-phase self-assembly technology. The method comprises the following steps of: dissolving Bi(NO3)3.5H2O and Fe(NO3)3.9H2O which serve as raw materials into distilled water, and regulating the pH value of the solution by using glacial acetic acid; preparing a film by using citric acid as a complexing agent, using a functionalized self-assembly single-layer film as a template and suspending the template on the surface of the solution in a mode that the functionalized side of the template is downward through reverse adsorption; drying at room temperature, preserving the heat for 10 minutes at the temperature of 300 DEG C to remove organic substances, preserving the heat at the temperature of 550 DEG C and annealing to prepare a crystallized bismuth ferrite functional film, performing ultraviolet irradiation and reverse adsorption, drying and annealing; and repeating the steps till the bismuth ferrite functional film with the dielectric property is prepared. The bismuth ferrite film with the dielectric property is prepared by combining the advantages of liquid-phase self-assembly through multiple times of reverse adsorption and layer-by-layer annealing.

The invention relates to a B-site Mn and Cu codoped high remanent polarization BiFeO3 film and a preparation method, the method comprises the following steps: dissolving bismuth nitrate, ferric nitrate, manganese acetate and cupric nitrate according to mol ratio of 1.05: [(0.92-0.98)-x]: (0.02-0.08):x in a mixed liquor of ethylene glycol monomethyl ether and acetic anhydride, then uniformly stirring to obtain a BiFeO3 precursor; wherein total metal ion concentration of the BiFeO3 precursor is 0.1-0.5mol / L, X is 0.01-0.03; performing spin coating of the BiFeO3 precursor on a FTO / glass substrate to prepare a wet membrane, baking the wet membrane to obtain a dry membrane, then annealing at 550 DEG C to obtain the crystalline state BiFeO3 film; cooling the crystalline state BiFeO3 film, and repeatedly making the crystalline state BiFeO3 film to reach a required thickness to obtain the B-site Mn and Cu codoped high remanent polarization BiFeO3 film. According to the invention, a sol gel technology is employed, the equipment requirement is simple, the film is prepared on large surface and surfaces with irregular shapes, the chemical component is accurate and controllable, and the regulation and control to its crystal structure can be carried out by codoping thereby the ferroelectric performance of the film is greatly increased.

Disclosed are a semiconductor arrangement, a method of manufacturing the same, and an electronic device including the same. According to an embodiment, a semiconductor arrangement may include a first semiconductor device and a second semiconductor device sequentially stacked on a substrate. Each of the first semiconductor device and the second semiconductor device may include: a first source / drain layer, a channel layer, and a second source / drain layer stacked in sequence, wherein the channel layer includes the first and second source / drain layers. a different semiconductor material for the drain layer; and a gate stack formed around the periphery of the channel layer.