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Memory device, manufacturing method thereof and electronic device comprising memory device

A storage device and storage gate technology, which is applied to semiconductor devices, electric solid state devices, circuits, etc., can solve the problems of difficulty in stacking multiple vertical devices, difficulty in controlling gate length, and increase in channel resistance, so as to improve device performance. , the effect of increasing storage density and low leakage current

Active Publication Date: 2018-04-06
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, for vertical devices, it is difficult to control the gate length, especially for single crystal channel materials
On the other hand, if a polycrystalline channel material is used, the channel resistance is greatly increased compared to single crystal material, making it difficult to stack multiple vertical devices, as this would result in an excessively high resistance

Method used

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  • Memory device, manufacturing method thereof and electronic device comprising memory device
  • Memory device, manufacturing method thereof and electronic device comprising memory device
  • Memory device, manufacturing method thereof and electronic device comprising memory device

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Embodiment Construction

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0020] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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Abstract

The invention discloses a memory device, a manufacturing method thereof and an electronic device comprising the memory device. According to an embodiment, the memory device may include a plurality offirst columnar active regions, a plurality of second columnar active regions, a plurality of layers of first memory gate stacks and a plurality of layers of second memory gate stacks; the first columnar active regions and the plurality of second columnar active regions are formed on a substrate and extend upwardly; the first columnar active regions and the plurality of second columnar active regions are respectively arranged as a first array and a second array; each first columnar active region includes source / drain layers and channel layers which are alternately stacked; corresponding channellayers in the first columnar active regions are substantially coplanar; corresponding source / drain layers in the first columnar active regions are substantially coplanar; each second columnar activeregion includes an integrally-extending active semiconductor layer; the plurality of layers of first memory gate stacks are substantially coplanar with the channel layers; the plurality of layers of first memory gate stacks surround the peripheries of the channel layers on corresponding planes respectively; and the plurality of layers of second memory gate stacks surround the peripheries of the second columnar active regions respectively.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and in particular, to a storage device based on a vertical type device, a manufacturing method thereof, and an electronic device including the storage device. Background technique [0002] In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device cannot be easily further scaled down. Unlike this, in a vertical type device, the source, gate, and drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are easier to scale down than horizontal devices. [0003] However, for vertical devices, it is difficult to control the gate length, especially for single crystal channel materials. On the other hand, if a polycrystalline channel mat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11556H01L27/11582H01L27/11597
CPCH10B53/30H10B41/27H10B43/30H10B41/30H10B51/20H10B43/27H10B41/50H10B43/50H10B51/50H01L29/40114H01L29/40117H01L29/40111H10B41/10H10B43/10H10B51/10
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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