Memory device, manufacturing method thereof, and electronic equipment including the same

A technology for storage devices and storage gates, applied in semiconductor devices, electrical solid state devices, circuits, etc., can solve problems such as difficulty in stacking multiple vertical devices, difficulty in controlling gate length, increase in channel resistance, etc., to improve device performance , increase the storage density, the effect of low leakage current

Active Publication Date: 2019-03-19
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, for vertical devices, it is difficult to control the gate length, especially for single crystal channel materials
On the other hand, if a polycrystalline channel material is use

Method used

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  • Memory device, manufacturing method thereof, and electronic equipment including the same
  • Memory device, manufacturing method thereof, and electronic equipment including the same
  • Memory device, manufacturing method thereof, and electronic equipment including the same

Examples

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Embodiment Construction

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0016] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...

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PUM

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Abstract

Disclosed are a storage device, a manufacturing method thereof, and electronic equipment including the storage device. According to an embodiment, a memory device may include a plurality of memory cell layers sequentially stacked on a substrate, each memory cell layer includes an array of memory cells, and the memory cells in each memory cell layer are along the stacking direction of the memory cell layers are substantially aligned with each other. Each memory cell includes: a first source/drain layer, a channel layer, and a second source/drain layer stacked in sequence, wherein the channel layer includes a semiconductor material different from that of the first and second source/drain layers; and A memory gate stack is formed around the periphery of the channel layer. The memory gates of the memory cells in the same memory cell layer are stacked into one body. For each storage unit, its first source/drain layer is integrated with the second source/drain layer of the corresponding storage unit in the lower layer, and its second source/drain layer is integrated with the first source/drain layer of the corresponding storage unit in the upper layer.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and in particular, to a storage device based on a vertical type device, a manufacturing method thereof, and an electronic device including the storage device. Background technique [0002] In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device cannot be easily further scaled down. Unlike this, in a vertical type device, the source, gate, and drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are easier to scale down than horizontal devices. [0003] However, for vertical devices, it is difficult to control the gate length, especially for single crystal channel materials. On the other hand, if a polycrystalline channel mat...

Claims

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Application Information

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IPC IPC(8): H01L27/115H01L27/11521H01L27/11556H01L27/11568H01L27/11582
CPCH10B41/27H10B51/20H10B43/27
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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