Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same

a semiconductor memory and charge retention technology, applied in the direction of semiconductor devices, electrical appliances, nanotechnology, etc., can solve the problems of high device integration difficulty, data erasure operation speed improvement difficulty, etc., and achieve excellent adhesiveness and excellent productivity

Inactive Publication Date: 2007-07-05
ASAHI GLASS CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0023] Namely, it is an object of the present invention to provide a floating gate type nonvolatile semiconductor memory device having high charge retention characteristic, and to provide a nonvolatile semiconductor memory device in which miniaturization and high integration of the device and increasing of the operation speed are possible, and further to provide a process for manufacturing such a nonvolatile semiconductor device with good repeatability.
[0048] This construction, in a case of utilizing the eighth and sixteenth aspects of the present invention, enables to realize a nonvolatile semiconductor memory device in which the charge retention layer of the nonvolatile semiconductor memory device having the above-mentioned characteristics can be suitably formed, can be realized since the sputtering method, among physical vapor deposition methods, particularly has such characteristics that it provides excellent adhesiveness to a foundation layer, it can form a dense film in which atoms constituting the film are strongly bonded, it enables wide selection of film-forming materials, and it is excellent in productivity with low film-forming cost.

Problems solved by technology

This problem causes various problems in the characteristic of the above-mentioned nonvolatile memory devices, such that miniaturization or high integration of the devices is difficult and that the improvement of the speed of data-writing operation or data-erasing operation is difficult.

Method used

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  • Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same
  • Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same
  • Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same

Examples

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example 1

[0097] The nonvolatile semiconductor memory device of this Example will be explained, referring to FIG. 2. A tunnel insulating film 2 was formed on a p-type semiconductor substrate 1. The tunnel insulating film 2 was formed on the surface of the semiconductor substrate 1 by subjecting the semiconductor substrate to thermal oxidation at 800° C. and had a thickness of 5 nm.

[0098] Then a charge retention layer 3 constituted by an insulating matrix 3b containing nano-particles 3a, was formed so as to have a thickness of 5 nm by a capacitively coupled magnetron sputtering method as described below. Metal Co having a work function of 5.0 eV was selected for the nano-particles and amorphous SiO2 having an electron affinity of 1.0 eV for the insulating matrix. In the sputtering step, a target composed of a SiO2 target having a diameter of 3 inches (7.62 cm) and Co chips of 5 mm square placed thereon, was employed. The amount of the Co chips was adjusted so that the chips occupy 20% of the ...

example 2

[0102] The nonvolatile semiconductor memory device of this example is explained, referring to FIG. 3. An SOI (Silicon On Insulator) substrate having a p-type SOI layer 1a, was employed for a p-type semiconductor substrate 1. An isolation was performed by a mesa process and boron was implanted to adjust the threshold voltage. The work function of the p-type SOI layer 1a was estimated to be 4.95 eV at this time. Then, a tunnel insulating film 2 was formed on the surface of the p-type SOI layer 1a. The tunnel insulating film 2 was formed by subjecting the semiconductor substrate to thermal oxidation at 800° C. and has a thickness of 3 nm.

[0103] Then, a charge retention layer 3 composed of an insulating matrix 3b containing nano-particles 3a was formed to have a thickness of 5 nm by a capacitively coupled magnetron sputtering method as follows. Metal Ru having a work function of 4.7 eV was selected for the material of the nano-particles, and AlN having a negative electron affinity was ...

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Abstract

There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.

Description

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION [0001] The present invention relates to a nonvolatile semiconductor memory device and its manufacturing process. In particular, the present invention relates to a structure in which particles with nano-scale consisting of at least one type of single-element substance or its compound are densely distributed in an insulating matrix. Further, the present invention relates to a nonvolatile semiconductor memory device having a charge retention layer with excellent retention characteristic by optimizing the work function or the electron affinity between the nano-particles and the insulating matrix, and by optimizing the distances between surfaces of adjacent nano-particles, and its manufacturing process realizing low cost and good reproducibility. DISCUSSION OF BACKGROUND [0002] Heretofore, as a recording medium in which a large amount of data can be memorized and rewritten, a memory device employing a semiconductor such as DRAM or SRAM, ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/336H01L21/3205
CPCH01L29/42332Y10S977/943
Inventor TAKATA, MASAAKIKOYANAGI, MITSUMASA
Owner ASAHI GLASS CO LTD
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