870 results about "Analogue circuits" patented technology

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

The invention discloses a process deviation-oriented analog circuit parameter optimization method, which comprises the following steps of: S1, carrying out multi-objective optimization on a given analog circuit under a nominal process condition, identifying and eliminating a design region with poor performance according to an optimization result, and carrying out clustering analysis to obtain an optimal design region; dividing the remaining high-quality areas into a plurality of initial trust areas; s2, modeling the finite Monte Carlo simulation data in the initial trust area by using a heterovariance Gaussian process model, capturing an average level and a change trend of circuit performance, and predicting behaviors of the circuit under process change; and S3, the required yield is kept while the performance is optimized, probability assurance is provided for the performance value by adopting the risk value, and a design point optimization set and a corresponding Pareto optimal solution set are finally obtained through multiple iterations in the optimization stage of considering the process change. According to the method, the high-quality Pareto optimal solution set meeting the yield constraint is found under the process change of unknown distribution, and the size of an analog circuit is optimized.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention discloses an early fault diagnosis method for an analog circuit based on subsequence division and Transform. According to the method, an analog circuit time domain response signal is taken as input, a multi-class fault data set constructed by combining PSpice simulation and a Monte Carlo method is divided through a sliding window to generate subsequences, and then local time sequence characteristics are extracted by using depth separable convolution and an SE module and resistance and capacitance fault sensitive frequency bands are adaptively enhanced; the method comprises the following steps: firstly, position coding is carried out on a device, then time sequence information which keeps cross-subsequence with position coding is embedded through token, a Transform encoder modeling global dependency relationship is input, meanwhile, a time sequence coupling effect generated by multi-device collaborative degradation is captured, and finally, multi-class fault diagnosis is completed through a full-connection fault diagnosis module. According to the method, weak fault features and cross-time slice long-range correlation caused by early degradation can be effectively recognized, and experimental results show that the method has high precision and good engineering application value under complex working conditions.

Disclosed in the present application are an analog circuit netlist division method and system based on reinforcement learning. The method comprises: acquiring an analog circuit netlist; performing feature extraction processing on the analog circuit netlist, so as to obtain circuit features; performing classification processing on the circuit features on the basis of a hierarchical reinforcement learning algorithm, so as to obtain a classification result; and performing function labeling processing on the classification result, so as to obtain a modular circuit netlist. By means of the present application, automatic identification and classification can be performed on an analog circuit in combination with machine learning, so as to better adapt to different types of circuits and problems, thereby improving the quality and efficiency of division. The present application can be widely applied to the technical field of circuit division.

The invention aims to provide a method and a system for realizing a built-in self-test code of a PCIE (Peripheral Component Interface Express) physical layer. The method comprises the following steps of: integrating PCIE BIST GEN module packaging data in a controller layer and sending the data to a physical coding sub-layer; the physical coding sub-layer codes the packaged data and sends the coded data to the physical medium adaptation layer; and the physical medium adaptation layer converts the coded data into serial data and transmits the serial data back to the controller layer. According to the invention, the BIST test assembly meeting the PIPE protocol requirement is embedded in the PCS layer, and compared with a traditional BIST test scheme, through early-stage simulation and post-silicon test data result analysis, not only can the electrical performance test requirement of an original analog circuit be met, but also the test coverage of the PCS layer is increased. And the full-stack coverage test from the physical signal to the protocol logic is realized.

The invention belongs to the technical field of integrated circuits, and particularly relates to an analog circuit yield optimization method under multiple environment angles based on a Bayesian neural network. According to the method, a Bayesian neural network (BNN) is used for carrying out synchronous modeling on yield and nominal performance under multiple environment angles, and yield optimization under the multiple environment angles is executed by embedding the BNN into a Bayesian optimization framework. The BNN model provided by the invention can better learn the correlation between the yield and the performance under different environmental angles, provides a strong modeling capability for the yield and the uncertainty thereof, and improves the yield optimization efficiency. Compared with other baseline methods, under the condition that the same target yield is achieved, the circuit simulation time cost can be saved by 45.3%, under the same circuit simulation time cost, a design point with the higher yield can be obtained, and the yield is improved by 3.2%.

The invention relates to a capacitor mismatch foreground calibration method suitable for an SARADC, and the method comprises the steps: S1, enabling an analog input signal, a random jitter signal and a dynamic element to be matched with each other, and jointly inputting the signals into a capacitive digital-to-analog converter; s2, comparing the output of the capacitive digital-to-analog converter with a reference point through a comparator, and storing to obtain an output digital code; s3, calculating an evaluation value of the corresponding output digital code; s4, obtaining an error between the actual output value and the reference output value estimation value; s5, iterating the capacitance weight and the random signal according to the size of the error by utilizing an LMS (Least Mean Square) algorithm; and S6, continuously changing the capacitance weight and the random signal to enable the error to be within an allowable range, and obtaining more accurate output. According to the invention, no additional analog circuit needs to be added for capacitor mismatch calibration, and parameters such as the significant bit number and the spurious-free dynamic range of the ADC are obviously improved.

The invention discloses an analog IC netlist layout collaborative optimization method and system based on a reinforcement learning algorithm, and the method comprises the steps: generating an initial netlist of an analog IC, and inputting the initial netlist into a pre-built simulation platform; generating an analog IC circuit layout according to the initial netlist of the analog IC, and performing simulation through a simulation platform; the reinforcement learning agent builds a graph neural network to execute an optimization task based on a pre-built analog IC netlist multilateral heterogeneous graph, generates an optimized analog IC netlist and sends the optimized analog IC netlist to the simulation platform; a new analog IC circuit layout is generated according to the optimized netlist of the analog IC, the simulation platform simulates the optimized netlist of the analog IC and the new analog IC circuit layout, and the analog IC circuit layout is further optimized through a reinforcement learning agent; and continuously interactively optimizing the reinforcement learning agent and the simulation platform until a final parameter combination meeting the performance index is obtained. According to the invention, the efficiency and performance of circuit optimization are greatly improved.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

According to the pure hardware PID current control system and method based on the direct current brushless motor provided by the invention, the negative voltage interference generated by electromagnetic induction is directly filtered in the bus current signal acquisition stage through the cooperation of the current sampling module and the bus negative voltage elimination module; the problem of signal distortion caused by negative voltage in a traditional sampling circuit is eliminated, and the current effective value detection precision is improved; the PID control module constructed based on pure hardware calculates a difference value between a target voltage and an actual voltage in real time through an analog circuit, and generates a proportional, integral and differential composite compensation signal, so that a PWM modulation circuit can adjust duty ratio output in real time according to the compensation signal, and it is ensured that a bus current of a motor driver is rapidly converged to a target value; the whole scheme does not need to depend on a microcontroller and a complex software algorithm, closed-loop current control is achieved through discrete devices, and the system cost is reduced.

The invention discloses a parameter determination method and device of an analog circuit, a medium and a product, and relates to the technical field of integrated circuit design. Local performance feedback and global topology perception of performance index parameters are used as input parameters, and pertinence and generalization ability of parameter adjustment are remarkably improved. Through a strategy function, a parameter candidate set of a target analog circuit is obtained, through multi-group sampling processing, variance of strategy gradient estimation is reduced, and training stability and convergence speed are improved. Depending on a value network is not needed, and training resource overhead is reduced. And applying the parameter candidate set output by the strategy function to the simulation processing scene to realize the accuracy of simulation processing evaluation. The target performance indexes are extracted from the simulation result, optimization of the performance indexes is achieved, the multiple target performance indexes are processed according to the multi-target reward function, balance selection and rejection are achieved in the multiple performance indexes, the parameter combination corresponding to the highest advantage value is obtained, and the reliability of the analog circuit parameter determination process is improved.

The invention provides a constant-power load analog circuit, a constant-power adjusting method and a rack-mounted load box, and belongs to the field of rack-mounted load boxs.The analog circuit comprises a rectifying circuit, a diverter, a power module, a fan module and a control and drive circuit, and the power module comprises at least one heating tube and at least one transistor. The control and drive circuit comprises a main control circuit, a voltage signal processing circuit, a current signal processing circuit, a power setting and display module and at least one IGBT drive circuit, the base electrode of the transistor is connected to the main control circuit through the IGBT drive circuit, and the power setting and display module is connected to the main control circuit and used for inputting a set power value. The main control circuit collects voltage and current of an external power supply, calculates a rated power value, calculates a signal duty ratio according to a set power value and the rated power value, outputs a PWM wave, controls on or off of a transistor through the IGBT driving circuit, dynamically adjusts actual output power of the load simulation circuit to be consistent with the set power value, and controls the load simulation circuit to work. And the power regulation precision of the load box is improved.

The invention discloses a crystal oscillator circuit fault classification technology based on a multi-source information fusion network, and belongs to the technical field of analog circuit fault diagnosis. Firstly, a multi-source data set of different measurement points of the crystal oscillator circuit is acquired; carrying out conversion from a time domain to a frequency domain on the data set by utilizing fast Fourier transform; extracting data fault features by using a convolutional neural network, and performing a trust distribution function under each piece of source data by using a softmax classifier; fusing different trust distribution functions under the multi-source data by adopting a D-S evidence theory to obtain a final diagnosis result and diagnosis probability output, and calculating cross entropy loss; and finally, training model parameters through back propagation to obtain a final diagnosis model. According to the method, the time-frequency transformation algorithm, the deep neural network algorithm and the information fusion algorithm are combined, a multi-source information fusion network is constructed, the defects of an existing diagnosis model in crystal oscillator circuit fault classification are overcome, and the accuracy and stability of crystal oscillator circuit fault diagnosis are remarkably improved.

The invention discloses a personal dosimeter capable of nuclide identification, and the dosimeter comprises a scintillation detector which is composed of a scintillation crystal and SiPM and captures an energy spectrum signal of a ray; the signal amplifier receives the voltage signal output by the SiPM and preprocesses and amplifies the voltage signal; the multichannel analyzer is used for receiving the amplified signal output by the signal amplifier and realizing energy spectrum acquisition in a target energy range; and the MCU receives the signals acquired by the multichannel analyzer and performs energy spectrum analysis. According to the invention, the scintillation detector based on SiPM and scintillation crystals is used, so that the small size and high sensitivity of the personal dosimeter are realized; according to the multi-channel analyzer, the multi-channel analyzer capable of setting the energy range is realized through the ADC and the comparator, and the design of a peripheral circuit is extremely simplified; the simplified nuclide identification method is designed based on prior information, the range of a nuclide library is narrowed, and the requirements of nuclide identification in a specified application scene for the computing power of a system and the complexity of an analog circuit are further reduced.

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

A method for automatic control of a simulation error in an analog circuit and a use thereof are provided. The method first determines a measurement object and acquires a simulation standard by simulating the measurement object. Then, the method performs simulation based on different parameters of a circuit netlist to acquire an electrical parameter and / or circuit performance evaluation indicator of the measurement object during a simulation process. The method forms a simulation sampling dataset based on a simulation option combination parameter and an error corresponding to the simulation standard. Finally, the method optimizes and analyzes the simulation sampling dataset based on an artificial intelligence algorithm to acquire a simulation option combination that meets a simulation error requirement and takes a least time. The solution achieves automatic selection of the simulation option combination, improving the accuracy of the simulation result.

The invention aims to provide the analog circuit frequency response flatness digital compensation calibration method which can reduce the hardware device requirement, the production process requirement and the production cost and meet the frequency response flatness requirement of low-frequency alternating current test equipment. The method comprises the following specific steps: S1, setting a frequency band range and extracting a plurality of groups of original data; s2, setting a sampling rate and an order; s3, generating a target frequency range, and setting a plurality of target frequency points; s4, extrapolating a frequency response curve and obtaining a frequency response value of a specific frequency; step S5, calculating frequency response characteristics according to the original data extracted in the step S1, and performing frequency response interpolation calculation of a plurality of target frequency points in a target frequency range based on a linear difference method to obtain a frequency response curve; s6, carrying out reciprocal processing on the frequency response curve to obtain a compensation curve; and S7, calculating calibration parameters according to the compensation curve. The method is applied to the technical field of electric signal processing.

The invention provides a zero-voltage starting control module, a driving circuit and an active clamping converter, and the module comprises a timing unit which carries out the timing of a first time length; the time length acquisition unit is used for acquiring the time length from the turn-off of the clamping tube to the complete release of the secondary inductive current of the transformer to obtain a second time length; the comparison unit is used for comparing the first duration with the second duration; and the dead time adjusting unit is used for adjusting the conduction time and the first duration of the clamping tube in the next period based on the comparison result of the current period so as to realize self-adaptive zero-voltage starting control. The circuit is realized by adopting a digital circuit, accurate control can be realized, the control range is relatively wide, zero-voltage conduction control is dynamically realized, the system efficiency is improved, the use of a capacitor in an analog circuit is reduced, and the area cost of a chip is reduced.

The invention relates to a distortion degree measuring system and method based on correlation operation, and the system comprises a signal source which is a to-be-measured signal source for outputting a mixed waveform comprising a fundamental wave and each harmonic component; the fundamental wave extraction module is used for separating and extracting a fundamental wave component of which the waveform is a single-frequency square wave from the signal to be detected; the phase-locked loop frequency multiplication module is used for receiving the fundamental component and locking and extracting a sine wave signal containing the fundamental component and a harmonic component through a phase-locked loop containing a programmable frequency divider; the correlator module is composed of a multiplier circuit and a low-pass filtering and amplifying circuit, receives a to-be-measured signal serving as an input signal and a sine wave signal serving as a reference signal, and outputs a direct-current component; and the single chip microcomputer is configured with the programmable frequency divider, samples the direct current component output by the correlator module, calculates the relative amplitude and the total harmonic distortion degree of the fundamental wave component and the harmonic component, and outputs the total harmonic distortion degree. The beneficial effects are that the measurement system and the signal processing method are suitable for signal harmonic analysis under a complex harmonic environment and a low signal-to-noise ratio condition, a high-performance processor and a computing power requirement are not needed, and the system takes an analog circuit as a main body and has the advantages of high measurement speed, high accuracy, low system cost and the like.

The invention relates to the technical field of circuit wiring, in particular to an AI-based circuit wiring system, method, medium and equipment, and the system comprises an input module, a preprocessing module, a deep learning module, a topology loss calculation module, a candidate layout generation module, a graphical user interface module, a man-machine interaction module and an output module. The input module is used for receiving each device of an analog circuit and physical size information thereof, and describing a description file of a topology constraint relationship between device pairs; the preprocessing module performs normalization processing on the size information of the device; the deep learning module is a graph structure neural network, and an output layer of the graph structure neural network outputs two-dimensional plane position coordinates corresponding to the devices; the topology loss calculation module defines a topology loss function and calculates an error value in a graph structure neural network training process, and the candidate layout generation module automatically generates a plurality of device candidate layout schemes meeting the topology loss function based on the trained graph structure neural network; the graphical user interface module is used for displaying candidate layout schemes and the error component value of each scheme; the man-machine interaction module provides a layout fine tuning function through a graphical user interface; the output module is used for outputting a final device layout scheme after manual fine tuning or automatic generation; according to the invention, the design efficiency and quality of the layout of the analog integrated circuit are improved, and the requirements of modern integrated circuit design for rapid iteration and efficient layout are met.

A method, system, and apparatus for determining a yield estimate for an integrated circuit are provided. The method includes the acts of generating a set of vectors of scaled parameter values, simulating an output of the circuit to identify a subset of the set of vectors, identifying a set of points on boundaries of failure regions in the parameter space, generating a set of sample points for each failure region. and determining a yield estimate based on the sets of sample points

The invention provides a current distribution method and an analog circuit, and the method comprises the steps: determining a distribution proportion constraint interval set for each battery cluster according to the total number of a plurality of battery clusters connected in parallel in a battery energy storage system, and determining a current distribution target proportion set for each battery cluster according to a battery cluster parameter, the current distribution target proportion is within the distribution proportion constraint interval, and the battery cluster parameters comprise at least one of the following items: the current residual capacity of the battery cluster, a capacity setting critical value and the distribution proportion constraint interval, and distributing current for each battery cluster according to the current distribution target proportion. According to the invention, it can be ensured that the battery clusters with different capacities are rapidly balanced in the operation process, and the stability and reliability of the battery energy storage system are improved.

The invention relates to an optical power detection circuit, system and method and a laser. The circuit comprises: an analog signal processing circuit configured to convert a laser pulse signal emitted by a laser into an analog circuit signal; a peak detection circuit configured to perform peak signal detection on the analog circuit signal output by the analog signal processing circuit and output a peak signal of the analog circuit signal; an integration circuit configured to perform integration processing on the analog circuit signal output by the analog signal processing circuit and output an integrated value signal of the analog circuit signal; and a microcontroller configured to receive the peak signal and the integrated value signal, and calculate an output parameter of the laser according to the peak signal and the integrated value signal. By adopting the method, the efficiency of optical power detection can be improved.

The invention discloses an analog circuit performance driving automatic wiring method based on multiple modes, and belongs to the technical field of integrated circuit design. According to the method, key information in circuit layout, physical interconnection and logic netlists is extracted by generating an input cost diagram containing horizontal, vertical and via hole wiring cost information and utilizing a multi-scale routing model fused by multi-modal features. Furthermore, the gradient of the input cost diagram to the circuit performance is calculated through back propagation of the neural network, and a wiring guidance diagram is generated through post-processing to guide subsequent detailed wiring based on an A * search framework and symmetric constraints. Finally, the method can improve the wiring precision, achieves the optimization of the performance of an analog circuit, and provides an efficient and intelligent wiring solution for the automatic design of an integrated circuit.

The invention belongs to the technical field of hardware and information security, and particularly relates to a digital PUF circuit based on an FPGA and a use method of the digital PUF circuit. In the PUF circuit, entropy source extraction and PUF response generation are separately processed, and the resistance value of a memristor in a high resistance state is collected through a memristor resistance value collection circuit; the resistance value distribution of each memristor in a high-resistance state has randomness, so that the high-resistance-state resistance value of the memristor can be used as an entropy source of the PUF circuit; a memristor-based entropy source is subjected to digital processing and is applied to a digital PUF circuit, resistance values of different memristors in a high-resistance state are randomly selected through digital chaotic signals, and finally PUF response is output by comparing the resistance values of the two memristors selected randomly in the high-resistance state. Compared with a traditional analog PUF circuit which is easily influenced by factors such as voltage fluctuation and device parameter drift, the digital PUF circuit based on the FPGA designed by the invention is higher in reliability and is not easily influenced by the factors such as the voltage fluctuation.

A current distribution method and an analog circuit, which can ensure that battery clusters with different capacities are quickly balanced during operation, thereby achieving the effect of improving the stability and reliability of a battery energy storage system. The method comprises: on the basis of the total number of battery clusters connected in parallel in a battery energy storage system, determining a distribution proportion constraint interval, which is set for each battery cluster (S101); on the basis of a battery cluster parameter, determining a target current distribution proportion, which is set for each battery cluster, wherein the target current distribution proportion falls within the distribution proportion constraint interval, and the battery cluster parameter comprises at least one of the following: the current remaining capacity of the battery cluster, a set critical capacity value, and the distribution proportion constraint interval (S102); and on the basis of the target current distribution proportions, distributing currents to the respective battery clusters (S103).