706 results about "Analogue circuits" patented technology

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

The invention discloses a process deviation-oriented analog circuit parameter optimization method, which comprises the following steps of: S1, carrying out multi-objective optimization on a given analog circuit under a nominal process condition, identifying and eliminating a design region with poor performance according to an optimization result, and carrying out clustering analysis to obtain an optimal design region; dividing the remaining high-quality areas into a plurality of initial trust areas; s2, modeling the finite Monte Carlo simulation data in the initial trust area by using a heterovariance Gaussian process model, capturing an average level and a change trend of circuit performance, and predicting behaviors of the circuit under process change; and S3, the required yield is kept while the performance is optimized, probability assurance is provided for the performance value by adopting the risk value, and a design point optimization set and a corresponding Pareto optimal solution set are finally obtained through multiple iterations in the optimization stage of considering the process change. According to the method, the high-quality Pareto optimal solution set meeting the yield constraint is found under the process change of unknown distribution, and the size of an analog circuit is optimized.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention discloses an early fault diagnosis method for an analog circuit based on subsequence division and Transform. According to the method, an analog circuit time domain response signal is taken as input, a multi-class fault data set constructed by combining PSpice simulation and a Monte Carlo method is divided through a sliding window to generate subsequences, and then local time sequence characteristics are extracted by using depth separable convolution and an SE module and resistance and capacitance fault sensitive frequency bands are adaptively enhanced; the method comprises the following steps: firstly, position coding is carried out on a device, then time sequence information which keeps cross-subsequence with position coding is embedded through token, a Transform encoder modeling global dependency relationship is input, meanwhile, a time sequence coupling effect generated by multi-device collaborative degradation is captured, and finally, multi-class fault diagnosis is completed through a full-connection fault diagnosis module. According to the method, weak fault features and cross-time slice long-range correlation caused by early degradation can be effectively recognized, and experimental results show that the method has high precision and good engineering application value under complex working conditions.

Disclosed in the present application are an analog circuit netlist division method and system based on reinforcement learning. The method comprises: acquiring an analog circuit netlist; performing feature extraction processing on the analog circuit netlist, so as to obtain circuit features; performing classification processing on the circuit features on the basis of a hierarchical reinforcement learning algorithm, so as to obtain a classification result; and performing function labeling processing on the classification result, so as to obtain a modular circuit netlist. By means of the present application, automatic identification and classification can be performed on an analog circuit in combination with machine learning, so as to better adapt to different types of circuits and problems, thereby improving the quality and efficiency of division. The present application can be widely applied to the technical field of circuit division.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

According to the pure hardware PID current control system and method based on the direct current brushless motor provided by the invention, the negative voltage interference generated by electromagnetic induction is directly filtered in the bus current signal acquisition stage through the cooperation of the current sampling module and the bus negative voltage elimination module; the problem of signal distortion caused by negative voltage in a traditional sampling circuit is eliminated, and the current effective value detection precision is improved; the PID control module constructed based on pure hardware calculates a difference value between a target voltage and an actual voltage in real time through an analog circuit, and generates a proportional, integral and differential composite compensation signal, so that a PWM modulation circuit can adjust duty ratio output in real time according to the compensation signal, and it is ensured that a bus current of a motor driver is rapidly converged to a target value; the whole scheme does not need to depend on a microcontroller and a complex software algorithm, closed-loop current control is achieved through discrete devices, and the system cost is reduced.

The invention discloses a parameter determination method and device of an analog circuit, a medium and a product, and relates to the technical field of integrated circuit design. Local performance feedback and global topology perception of performance index parameters are used as input parameters, and pertinence and generalization ability of parameter adjustment are remarkably improved. Through a strategy function, a parameter candidate set of a target analog circuit is obtained, through multi-group sampling processing, variance of strategy gradient estimation is reduced, and training stability and convergence speed are improved. Depending on a value network is not needed, and training resource overhead is reduced. And applying the parameter candidate set output by the strategy function to the simulation processing scene to realize the accuracy of simulation processing evaluation. The target performance indexes are extracted from the simulation result, optimization of the performance indexes is achieved, the multiple target performance indexes are processed according to the multi-target reward function, balance selection and rejection are achieved in the multiple performance indexes, the parameter combination corresponding to the highest advantage value is obtained, and the reliability of the analog circuit parameter determination process is improved.

The invention discloses a crystal oscillator circuit fault classification technology based on a multi-source information fusion network, and belongs to the technical field of analog circuit fault diagnosis. Firstly, a multi-source data set of different measurement points of the crystal oscillator circuit is acquired; carrying out conversion from a time domain to a frequency domain on the data set by utilizing fast Fourier transform; extracting data fault features by using a convolutional neural network, and performing a trust distribution function under each piece of source data by using a softmax classifier; fusing different trust distribution functions under the multi-source data by adopting a D-S evidence theory to obtain a final diagnosis result and diagnosis probability output, and calculating cross entropy loss; and finally, training model parameters through back propagation to obtain a final diagnosis model. According to the method, the time-frequency transformation algorithm, the deep neural network algorithm and the information fusion algorithm are combined, a multi-source information fusion network is constructed, the defects of an existing diagnosis model in crystal oscillator circuit fault classification are overcome, and the accuracy and stability of crystal oscillator circuit fault diagnosis are remarkably improved.

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

A method for automatic control of a simulation error in an analog circuit and a use thereof are provided. The method first determines a measurement object and acquires a simulation standard by simulating the measurement object. Then, the method performs simulation based on different parameters of a circuit netlist to acquire an electrical parameter and / or circuit performance evaluation indicator of the measurement object during a simulation process. The method forms a simulation sampling dataset based on a simulation option combination parameter and an error corresponding to the simulation standard. Finally, the method optimizes and analyzes the simulation sampling dataset based on an artificial intelligence algorithm to acquire a simulation option combination that meets a simulation error requirement and takes a least time. The solution achieves automatic selection of the simulation option combination, improving the accuracy of the simulation result.

The invention aims to provide the analog circuit frequency response flatness digital compensation calibration method which can reduce the hardware device requirement, the production process requirement and the production cost and meet the frequency response flatness requirement of low-frequency alternating current test equipment. The method comprises the following specific steps: S1, setting a frequency band range and extracting a plurality of groups of original data; s2, setting a sampling rate and an order; s3, generating a target frequency range, and setting a plurality of target frequency points; s4, extrapolating a frequency response curve and obtaining a frequency response value of a specific frequency; step S5, calculating frequency response characteristics according to the original data extracted in the step S1, and performing frequency response interpolation calculation of a plurality of target frequency points in a target frequency range based on a linear difference method to obtain a frequency response curve; s6, carrying out reciprocal processing on the frequency response curve to obtain a compensation curve; and S7, calculating calibration parameters according to the compensation curve. The method is applied to the technical field of electric signal processing.

The invention relates to a distortion degree measuring system and method based on correlation operation, and the system comprises a signal source which is a to-be-measured signal source for outputting a mixed waveform comprising a fundamental wave and each harmonic component; the fundamental wave extraction module is used for separating and extracting a fundamental wave component of which the waveform is a single-frequency square wave from the signal to be detected; the phase-locked loop frequency multiplication module is used for receiving the fundamental component and locking and extracting a sine wave signal containing the fundamental component and a harmonic component through a phase-locked loop containing a programmable frequency divider; the correlator module is composed of a multiplier circuit and a low-pass filtering and amplifying circuit, receives a to-be-measured signal serving as an input signal and a sine wave signal serving as a reference signal, and outputs a direct-current component; and the single chip microcomputer is configured with the programmable frequency divider, samples the direct current component output by the correlator module, calculates the relative amplitude and the total harmonic distortion degree of the fundamental wave component and the harmonic component, and outputs the total harmonic distortion degree. The beneficial effects are that the measurement system and the signal processing method are suitable for signal harmonic analysis under a complex harmonic environment and a low signal-to-noise ratio condition, a high-performance processor and a computing power requirement are not needed, and the system takes an analog circuit as a main body and has the advantages of high measurement speed, high accuracy, low system cost and the like.

The invention relates to the technical field of circuit wiring, in particular to an AI-based circuit wiring system, method, medium and equipment, and the system comprises an input module, a preprocessing module, a deep learning module, a topology loss calculation module, a candidate layout generation module, a graphical user interface module, a man-machine interaction module and an output module. The input module is used for receiving each device of an analog circuit and physical size information thereof, and describing a description file of a topology constraint relationship between device pairs; the preprocessing module performs normalization processing on the size information of the device; the deep learning module is a graph structure neural network, and an output layer of the graph structure neural network outputs two-dimensional plane position coordinates corresponding to the devices; the topology loss calculation module defines a topology loss function and calculates an error value in a graph structure neural network training process, and the candidate layout generation module automatically generates a plurality of device candidate layout schemes meeting the topology loss function based on the trained graph structure neural network; the graphical user interface module is used for displaying candidate layout schemes and the error component value of each scheme; the man-machine interaction module provides a layout fine tuning function through a graphical user interface; the output module is used for outputting a final device layout scheme after manual fine tuning or automatic generation; according to the invention, the design efficiency and quality of the layout of the analog integrated circuit are improved, and the requirements of modern integrated circuit design for rapid iteration and efficient layout are met.

A method, system, and apparatus for determining a yield estimate for an integrated circuit are provided. The method includes the acts of generating a set of vectors of scaled parameter values, simulating an output of the circuit to identify a subset of the set of vectors, identifying a set of points on boundaries of failure regions in the parameter space, generating a set of sample points for each failure region. and determining a yield estimate based on the sets of sample points

The invention discloses an analog circuit performance driving automatic wiring method based on multiple modes, and belongs to the technical field of integrated circuit design. According to the method, key information in circuit layout, physical interconnection and logic netlists is extracted by generating an input cost diagram containing horizontal, vertical and via hole wiring cost information and utilizing a multi-scale routing model fused by multi-modal features. Furthermore, the gradient of the input cost diagram to the circuit performance is calculated through back propagation of the neural network, and a wiring guidance diagram is generated through post-processing to guide subsequent detailed wiring based on an A * search framework and symmetric constraints. Finally, the method can improve the wiring precision, achieves the optimization of the performance of an analog circuit, and provides an efficient and intelligent wiring solution for the automatic design of an integrated circuit.

The invention discloses a low-power-consumption dynamic voltage control method and a low-power-consumption dynamic voltage control circuit, the low-power-consumption dynamic voltage control circuit comprises an analog circuit module and a digital circuit module which are arranged in a top module unit of a chip, and the analog circuit module comprises an OSC clock generation circuit which is used for generating a clock required by the digital circuit module. And the digital circuit module digit comprises a low-power-consumption dynamic voltage control circuit. According to the invention, the function of high-dynamic real-time adjustment of the voltage control code with extremely low power consumption is realized through pre-opening and pre-closing of the clock.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an apparatus is provided for adaptive signal conditioning for biopotential acquisition. The apparatus includes an analog circuit configured to amplify biopotential signals, and a mixed-signal circuit (e.g., which can include an adaptive digital algorithm) coupled to the analog circuit and configured to suppress aggressor signals such as baseline wandering signals and power-line-induced noise in the biopotential signals before amplification of the biopotential signals.

The invention discloses a low-cost soft error reinforcement method based on an approximate triple modular redundancy unit. The method comprises the following steps: establishing an approximate library: establishing an approximate gate unit for a basic gate unit of a to-be-reinforced circuit, and integrally establishing an approximate gate unit library; software modeling: acquiring basic information of each standard gate unit in the circuit, and evaluating the performance of the circuit according to a soft error propagation physical model so as to perform software modeling; and approximate reinforcement: selecting a gate unit in a to-be-reinforced circuit in a semi-directional manner based on improved dynamic adjustment NSGA-II to replace the gate unit with an approximate gate unit in an approximate library, simulating circuit performance indexes through an estimator, performing multi-target optimization solution, obtaining an optimal compromise of area, power consumption and soft error rate through iteration, and giving an approximate reinforcement scheme. The method has high efficiency, practicability and universality, can be used for guiding low-cost soft-error-tolerant approximate reinforcement of various high-reliability structures such as triple modular redundancy (TMR) and the like, and can adapt to multi-scene and multi-requirement circuit reinforcement design.

The invention belongs to the technical field of analog circuits, and particularly relates to a high-order compensation low-temperature-coefficient band-gap reference circuit based on a substrate bias technology. The high-order compensation band-gap reference circuit is characterized in that a substrate bias technology is used in the high-order compensation band-gap reference circuit, a temperature term highly fitted with a high-order nonlinear temperature term of base-emitter voltage VBE of a bipolar transistor is generated through substrate bias of an MOS tube in a sub-threshold region for temperature compensation, and the temperature coefficient of output voltage is greatly reduced; the circuit introduces trimming current to be injected into the resistor (R3), error trimming is achieved, trimming is easy, and the problem of temperature coefficient change caused by various non-ideal factors can be solved conveniently.

The embodiment of the invention relates to the technical field of sitting posture detection, in particular to a sitting posture detection method, device, equipment and system and a storage medium. The sitting posture detection method is applied to sitting posture detection equipment, the sitting posture detection equipment is installed on a seat, a preset number of pressure sensors are arranged at preset positions of the seat respectively, and the sitting posture detection method comprises the steps that analog signals collected by the pressure sensors are obtained, the analog signals pass through an amplification circuit, a filtering circuit and other analog circuits, and the analog signals are converted into the sitting posture detection equipment; digital signals used for sitting posture detection and identification are obtained after digital-to-analog conversion processing; determining a current sitting posture feature of the to-be-detected object according to the digital signal; and detecting the current sitting posture characteristics based on a sitting posture detection algorithm, and determining abnormal sitting posture information of the to-be-detected object according to a detection result. According to the method, the accuracy and the cost of sitting posture detection and the use convenience of the user can be considered.

The invention provides a digital-analog hybrid simulation method, platform, equipment, medium and product, and belongs to the technical field of integrated circuits, the method comprises the following steps: constructing a to-be-simulated analog circuit module, determining simulation excitation and target performance required by the analog circuit module, the simulation excitation comprises at least one ideal power supply waveform, at least one ideal clock waveform, at least one ideal control signal waveform and at least one ideal signal waveform; and performing joint simulation on the analog circuit module according to the simulation excitation, if the performance of the analog circuit module accords with the target performance, completing simulation, otherwise, adjusting the analog circuit module, and returning to execute the step of performing joint simulation on the analog circuit module according to the simulation excitation until the performance of the adjusted analog circuit module accords with the target performance. According to the simulation excitation of the waveform mode, the simulation circuit module is subjected to joint simulation so as to realize simulation in a simulation environment, and the simulation precision is effectively improved.

The embodiment of the invention provides a spurious emission elimination circuit, a spurious emission elimination method and electronic equipment. The spurious emission elimination circuit comprises a signal transmission branch and at least one spurious emission simulation circuit, the signal transmission branch is used for receiving the input signal and the at least one target stray analog signal, and performing stray elimination on the input signal based on the at least one target stray analog signal to obtain an output signal; the stray simulation circuit is used for receiving corresponding stray simulation information and output signals; generating an initial spurious simulation signal based on the spurious simulation information; and performing phase correction on the initial spurious analog signal based on the output signal to generate a target spurious analog signal.

A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.

The present invention discloses an automatic layout generation method. First, for a process library PDK specified by an analog circuit or a mixed-analog circuit, a cell library compiler AcellGen is used to generate the minimum analog unit Acell of each circuit component required for automatic layout. Then, each parameterized unit Pcell in a schematic diagram constructed using the parameterized unit Pcell is replaced with the corresponding minimum analog unit Acell. Then, based on the currently obtained schematic diagram, a corresponding circuit netlist is generated, and the Acell used in the schematic diagram is placed in the same schematic to extract a GDS file. Finally, based on the circuit netlist, GDS and the minimum analog unit of each circuit component required for automatic circuit layout, an automatic place and route tool (PNR) is used to perform final layout generation. The method has the advantages that it can be used for the layout design of analog circuits or mixed-analog circuits, the layout area is small, and no manual intervention is required when performing layout design on analog circuits or mixed-analog circuits, so the efficiency is high.

The invention discloses a closed-loop control method and device for a single transmitting side analog circuit of a wireless power transmission system, and the method comprises the steps: constructing a power transmission structure of the wireless power transmission system based on an SS-type two-coil wireless power transmission topology and an E-type power amplifier, and carrying out the power transmission; obtaining a voltage signal and a current signal by using a signal detection circuit; inputting the signal into a receiving side information back calculation circuit to obtain a coupling coefficient of a primary side coil and a secondary side coil and the size of a load; the duty ratio when the power transmission structure of the wireless power transmission system has the optimal transmission efficiency and output power is obtained through the transmitting side switching tube control structure, control square waves of the E-type power amplifier switching tube are generated according to the duty ratio, the control square waves are sent into the switching tube driving circuit, the control square waves are amplified, and the power transmission efficiency of the E-type power amplifier switching tube is improved. And opening and closing of the switch tube are controlled to complete closed-loop control. The device is simple in structure, high in efficiency, low in cost and wide in application range, and has good practical application value.

The invention discloses an ultrasonic thickness measuring method, which comprises the following steps that: a CPU (Central Processing Unit) controls a high-voltage pulse transmitting unit to generate a transmitting signal, an ultrasonic probe converts the signal into an ultrasonic signal, the ultrasonic signal enters the surface of a measured workpiece, passes through the workpiece, reaches the other surface and is reflected back to the ultrasonic probe, and the ultrasonic probe captures the echo signal and converts the echo signal into an electric signal; after being filtered and amplified by the analog circuit unit, the electric signal is converted into a digital signal through the ADC, and further filtering, averaging, detection and compression processing are completed by the FPGA; and the CPU verifies the effectiveness of the echo signal, performs automatic gain adjustment, and calculates the thickness value of the measured workpiece. By optimizing parameter configuration and a processing flow in an ultrasonic detection process, accurate control and data processing of ultrasonic waves are realized, and the thickness of a measured workpiece can be accurately measured; the method is mainly based on CPU development, the requirement for the FPGA in the development process is reduced, the development flexibility is improved, and the product cost is reduced.