317 results about "Analogue circuits" patented technology

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

A method, system, and apparatus for determining a yield estimate for an integrated circuit are provided. The method includes the acts of generating a set of vectors of scaled parameter values, simulating an output of the circuit to identify a subset of the set of vectors, identifying a set of points on boundaries of failure regions in the parameter space, generating a set of sample points for each failure region. and determining a yield estimate based on the sets of sample points

The invention belongs to the technical field of stability compensation circuits, and particularly relates to a stability compensation circuit structure of a high-speed operational amplifier, which is characterized by comprising a function module, a first control module, a second control module, a third control module, a fourth control module and a fourth control module, and the function module comprises an input stage, a differential common-base gain stage, a common-base level converter module and an output stage, and the stability compensation assembly comprises a dual-frequency load unit which is matched with the functional module and comprises a low-frequency load branch and a high-frequency load branch which are connected in parallel. Through the synergistic effect of the double-frequency load unit and the pole regulation and control capacitor, gain segmentation regulation and control of low-frequency high gain and high-frequency fast attenuation are achieved, the open-loop gain of the operational amplifier breaks through the limitation of 30dB of an existing HBT single-stage operational amplifier, and meanwhile the problem that high-frequency phase shift changes too fast is effectively restrained; through simulation verification, the phase margin can reach 67 degrees, the stability requirement of 45-60 degrees and above of an analog circuit is met, and the core contradiction that the high-gain bandwidth and the phase margin of an HBT device are difficult to balance is thoroughly overcome.

The invention provides a circuit design-process collaborative optimization method, a preparation method and a circuit based on an edge contact two-dimensional transistor, and aims at remarkably improving the load linearity, the output resistance and the switching stability of the two-dimensional transistor by adopting an edge contact process and optimizing the geometric parameters of the transistor according to the performance requirements of an analog circuit. The method specifically comprises the optimization design of the edge contact transistor, the characterization and improvement method of the load performance, and the system integration and application of the edge contact transistor in a high-performance analog circuit module. The invention provides a complete solution from transistor-level process optimization to circuit-level performance improvement, and provides a key technical path for design and manufacturing of high-linearity and high-stability analog and mixed signal integrated circuits based on novel two-dimensional semiconductors.

This application relates to the field of integrated circuit automated design technology, and particularly to a method, apparatus, and electronic device for optimizing transistor layout in analog circuits. The method includes: acquiring a device group layout diagram of transistors in an analog circuit; encoding the device group layout diagram into a character array; generating an initial parent population based on the character array; determining the genotype of the initial parent population for evolutionary iteration based on the character array; iterating the initial parent population based on its genotype, performing multi-objective evaluation on the current parent population based on offspring individuals during each iteration, until a preset number of iterations is reached; the current parent population includes one of the initial parent population and one of the evolved parent populations; and determining the optimization result of the device group layout diagram based on the last evolved parent population. This solves the problem in related technologies where transistor layout in analog circuits is difficult to balance device electrical matching performance with layout area and wiring complexity.

The invention provides a multi-agent reinforcement learning optimization method of an analog circuit and a related device. The method comprises the following steps: setting an ideal performance parameter group of the analog circuit; clustering the components according to the transient current curves of the components to obtain a plurality of component groups; configuring an intelligent agent for each component group, and enabling the intelligent agent to output a circuit parameter value according to the ideal performance parameter group; applying the circuit parameter value to a simulation circuit for simulation to obtain a simulation circuit performance value; updating the intelligent agent according to the simulation circuit performance value and a preset target performance value to obtain a target intelligent agent; the elements are clustered by analyzing the actual current characteristics of the circuit under transient response, so that the elements with similar functions are divided to the same agent, thereby breaking the limitation of a physical module, realizing parameter decoupling and collaborative optimization, and improving the convergence efficiency.

The invention discloses a heuristic-based iterative legalization method and system for an analog circuit layout, and the method comprises the steps: dividing layout groups according to a special structure and an array module in a layout based on the initial layout of the layout containing overlapped devices or modules; constructing a constraint graph for describing the relative position relationship between the layout groups, and solving symmetric constraint conflicts in the layout so as to ensure that all symmetric constraints are met; performing simulation processing on a non-overlapping constraint, a minimum area constraint and a minimum spacing constraint through a code simulation solver to generate an initial legal layout; and iteratively adjusting the constraint graph based on a heuristic method, identifying a suspicious group and adjusting the constraint edge of the suspicious group, and re-verifying and repairing the symmetric constraint after each adjustment until the layout area converges. According to the method, the symmetric constraint is synchronously verified and repaired in each iterative optimization, so that the layout area is minimized on the premise of ensuring the layout legality, and the solving efficiency is greatly improved at the same time.

The application relates to the fields of signal processing, image processing and communication engineering, and particularly relates to a real-time sparse signal reconstruction method based on an analog circuit, which comprises the following steps: acquiring an observation signal and an observation matrix; based on the observation signal and the observation matrix, an analog circuit is constructed; the numerical value of the observation signal is converted into a corresponding electric signal and applied to the input end of the analog circuit; the analog circuit is powered on and operated to a steady state, the steady-state voltage values of a plurality of predetermined nodes in the analog circuit are measured, and the measured steady-state voltage values are output as the reconstruction values of the sparse signal. The application adopts a technical path of a full-analog computing system architecture, and aims at a sparse signal reconstruction problem, converts a key mathematical model (specifically, an equation group represented by KKT conditions) in a solving process of the problem into a circuit physical structure, and outputs an optimal solution through a steady-state response of the circuit in one step.

This invention discloses a method, apparatus, medium, and device for parameter optimization of analog circuits, relating to the field of analog circuit technology. The invention automatically identifies current paths through a search algorithm to deeply analyze the circuit topology, determine the symmetry structure in the analog circuit, and constructs symmetry constraints based on the identical optimization parameters of electrical components within the symmetry structure. Simultaneously, it transforms the product of the transistor's gate width and the number of parallel connections into the total width and sets the optimization boundary. This combination reduces the dimensionality of the optimization variables while ensuring that the parameter optimization process conforms to the layout design of the analog circuit. Furthermore, it combines a population mutation algorithm and a non-dominated sorting genetic algorithm with an elitist strategy to perform iterative optimization within the constructed efficient search space, significantly improving the convergence speed of analog circuit parameter optimization, reducing computational costs, and enhancing the practicality of the analog circuit parameter optimization method.

The invention relates to a sensing and control device (40) and method for a weight measuring device (30) comprising a loading unit for loading material to be weighed. In order to be able to measure accurately with less expensive components, the sensing and control device comprises an analog circuit (50) and a control circuit (60). The analog circuit (50) is configured to receive a weight measuring signal, to convert the received weight measuring signal into a first voltage signal, to subtract a second voltage signal from the first voltage signal when the loading unit is loaded with material to be weighed to generate a third voltage signal representing the weight of the material to be weighed, the second voltage signal representing the weight of at least the loading unit not loaded with material to be weighed. The control circuit (60) is configured to receive the first voltage signal when the loading unit is not loaded with material to be weighed, to convert the first voltage signal into a first digital signal, and to generate a pulse width modulation, PWM, signal having a pulse width, the pulse width representing the weight measured by the weight measuring device when the loading unit is not loaded with material to be weighed, and the control circuit is further configured to convert the third voltage signal into a second digital signal representing a weight measurement of the material to be weighed. The analog circuit (50) is configured to generate the second voltage signal from the PWM signal generated by the control circuit, wherein the voltage level of the second voltage signal is proportional to the pulse width of the PWM signal.

There is provided an analog circuit comprising: a plurality of analog functions, which are divided into at least two groups of analog functions, and an interconnection structure configured to interconnect the plurality of analog functions so as to enable transfer of both voltage and current signals between analog functions among the plurality of analog functions. The interconnection structure comprises at least two hierarchy levels of interconnections, wherein a local-bus hierarchy level is configured to interconnect analog functions of a respective group, and a global-bus hierarchy level is configured to interconnect analog functions of the plurality of groups. The local-bus hierarchy level comprises voltage signal lines for transferring voltage signals and / or current signal lines for transferring current signals, and the global-bus hierarchy level comprises voltage signal lines for transferring voltage signals and / or current signal lines for transferring current signals.

The application provides a rail transit vehicle electrical cabinet maintenance practical training device, which comprises an upper computer and a plurality of simulation relays; the upper computer is used for generating a control instruction according to a maintenance practical training requirement and sending the control instruction to the plurality of simulation relays; the simulation relay comprises a controller and at least one contact simulation circuit; the conduction or cutoff of the contact simulation circuit is determined based on the output level of the output pin controlled by the controller; the simulation relay is used for analyzing the received control instruction based on the controller and controlling the output pin to output a high level or a low level based on the analysis result to control the conduction or cutoff state of the contact simulation circuit and simulate the maintenance practical training requirement. By adopting the controller plus the contact simulation circuit to construct the simulation relay, various fault states can be flexibly injected, and the safety and efficiency of the practical training are greatly improved.

The application relates to a Polar code decoding simulation circuit implementation method, system, equipment and medium based on a memory-computing integrated device, and the method comprises the following steps: obtaining a Polar code sparse check matrix and a corresponding probability graph model according to a received Polar code; obtaining an initial log-likelihood ratio of each variable node in the probability graph model; dividing a memory-computing integrated device array into an input part, an output part, an iteration part and a check part according to the Polar code sparse check matrix, and configuring the resistance state of the cross nodes in each part; loading the initial log-likelihood ratio into the input part of the memory-computing integrated device array and keeping it, and the initial input of other parts is 0; checking and iteratively calculating the calculation results output by the iteration part, the check part and the output part in the memory-computing integrated device array by using a peripheral circuit, and outputting a final decoding result after the check condition is met. The application can be widely applied in the field of decoding technology.

A system may comprise hardware and software configured to perform computing functions that mimic at least one computing function of a human brain, wherein the hardware and software comprises: analog circuitry configured to perform signal processing of neural signals obtained from living brain tissue using at least one sensor, a computer system comprising a processor, memory accessible by the processor, and computer program instructions stored in the memory and executable by the processor digital circuitry and software configured to process the obtained neural signals to generate a representation of a brain function from the obtained neural signals, and to generate parameters for use by analog and digital circuitry to perform computing functions that mimic at least one computing function of a human brain, and the analog and digital circuitry configured to use the generated parameters to perform computing functions that mimic at least one computing function of a human brain.

This invention provides a method for constructing and implementing a memristor-based chaotic synchronization system using FPGA circuits, comprising the following steps: Step 1, constructing the memristor chaotic synchronization system; Step 2, discretizing the memristor chaotic synchronization system to obtain discretized equations; Step 3, designing the various modules of the FPGA chaotic signal generator and converting the discretized equations into a hardware design language; Step 4, designing based on a state machine to solve the chaotic sequence; Step 5, simulating and verifying the designed program at the board level, and analyzing the implementation effect. This invention incorporates a memristor into the chaotic synchronization system, giving it more complex dynamic behavior and noise immunity, enabling it to reach synchronization faster and achieve stable error convergence. This solution addresses the shortcomings of current chaotic systems using analog circuits, such as unstable signals and susceptibility to external environmental interference, and can resist temperature changes and electromagnetic interference, generating high-quality chaotic signals.

A device may include a first plurality of electronic devices comprising a plurality of ports operable to facilitate communications via a plurality of lanes; a second plurality of electronic devices operable to communicate with the first plurality of electronic devices via the plurality of lanes; and a third plurality of electronic devices operable to communicate with the second plurality of electronics devices via a plurality of connections.

The application discloses a kind of invalid module identification method of smart meter integrated circuit, obtains the netlist file of smart meter integrated circuit, bypass device is obtained first by direct analysis method, then device and network node are used to model analog circuit to obtain device-node matrix, based on adjacency matrix calculation to obtain the reachable matrix of device, finally analyze the device name in the output of all isolated circuits of reachable matrix, complete the identification of all invalid modules.The application identifies bypass device and isolated circuit in integrated circuit by analyzing smart meter integrated circuit, provides basis for simplifying fault injection of integrated circuit, saves fault injection time.

The invention discloses an analog circuit and device for network cable testing, is applied to the technical field of electronic testing, and is used for solving the technical problem that the simulation effect of current network cable simulation equipment is not reliable. The analog circuit for network cable testing comprises a first circuit board, a second circuit board and a third circuit board, the second circuit board is connected with the third circuit board through the first circuit board, and a plurality of signal attenuation units are arranged between the first circuit board and the second circuit board. The signal attenuation unit comprises capacitor components, an upper resistor component and a lower resistor component, two ends of each capacitor component are respectively connected with different pins of the second circuit board in a one-to-one correspondence manner, one end of each capacitor component is further connected with one end of the upper resistor component, the other end of each capacitor component is further connected with one end of the lower resistor component, and the other end of each capacitor component is connected with the other end of the lower resistor component. The other end of each upper resistor assembly and the other end of each lower resistor assembly are connected with different pins of the first circuit board in a one-to-one correspondence manner.

The invention discloses a silicon carbide power module parallel current sharing device and an electric vertical take-off and landing aircraft, which are applied to the technical field of aviation power electronics and are used for solving the problems of poor real-time performance and reliability of the silicon carbide power module parallel current sharing device in the prior art. The method specifically comprises the following steps: a current sampling module collects branch current of each silicon carbide power module and correspondingly outputs a sampling voltage signal of each silicon carbide power module; the simulation error processing module correspondingly generates error adjusting voltage related to the current deviation of each branch through an internal hardware simulation circuit; and the gate driving adjustment module adjusts the reference ground potential of the corresponding gate driving chip according to the received error adjustment voltage. Through full-hardware and software-intervention-free simulation negative feedback closed-loop control, top-speed, automatic and self-adaptive current-sharing adjustment of the silicon carbide power modules connected in parallel is realized, and the device is insensitive to noise, so that the reliability of long-term operation is improved.

The application discloses a kind of sensing transducer and its voltage signal processing circuit, belong to the field of transducer, for using analog circuit to realize for sensor voltage signal segmented calibration, solved the problem that voltage signal is difficult to maintain higher signal accuracy under strong interference environment.Considering that the way of segmented calibration can improve the accuracy of sensor output voltage signal, and analog circuit has strong anti-interference ability, the segmented identification circuit of the application can deliver voltage signal to the segmented calibration circuit corresponding to the voltage value interval to which the voltage signal belongs, so that the segmented calibration circuit can multiply the received voltage signal by a predetermined slope and add a predetermined intercept, and output after signal conditioning circuit, so as to realize the segmented calibration of voltage signal, and each part of circuit is analog circuit, has strong anti-interference ability, so that voltage signal can maintain higher signal accuracy under strong interference environment, widen the application scenario of sensing transducer.

An analogue circuit design apparatus is configured to receive information representing electrical requirements for the analogue circuit, identify a plurality of potential layout techniques such as symmetrical, common centroid, and interdigitated layout technique, select one of the potential layout technique as the current selected layout technique, and determine physical properties of the analogue circuit based on the electrical requirements and the current selected layout technique. The analogue circuit design apparatus is configured to determine whether the current selected layout technique and determined physical properties of the analogue circuits meet the electrical requirements, and in the event that they do meet the electrical requirements, produce and output a design, or if they do not meet the electrical requirements, to repeat the process with a different selected layout technique as the current selected layout technique.

The embodiment of the application provides an audio low-frequency signal gain control circuit and a related device, which comprise an input processing sub-circuit, a non-dynamic low-frequency signal processing sub-circuit, a dynamic low-frequency signal processing sub-circuit, a signal synthesis sub-circuit, an adaptive gain control sub-circuit and a bass speaker. The input processing sub-circuit is used for pre-processing an input stereo audio signal to obtain a first audio low-frequency signal; the non-dynamic low-frequency signal processing sub-circuit is used for processing the first audio low-frequency signal to obtain a non-dynamic audio low-frequency signal; the dynamic low-frequency signal processing sub-circuit is used for separating a dynamic audio low-frequency signal; the signal synthesis sub-circuit is used for merging the non-dynamic audio low-frequency signal and the dynamic audio low-frequency signal to obtain an audio low-frequency signal; the adaptive gain control sub-circuit is used for gain control on the audio low-frequency signal; and the bass speaker is used for outputting the audio low-frequency signal. In this way, the adaptive gain on the audio low-frequency signal is realized through an analog circuit.

This invention provides an automatic method and system for generating analog circuits. The circuit partitioning step divides the radio frequency (RF) circuit into multiple circuit units. The circuit segmentation step converts each circuit unit into multiple circuit segments. Each circuit segment includes at least one main component data and at least one peripheral component data. The main component model establishment step establishes a main component model, which corresponds to the main component data of each circuit segment. The circuit segment model establishment step establishes a circuit segment model, which corresponds to each circuit segment. The model combination step combines the main component model corresponding to each circuit segment with the circuit segment model to generate the analog circuit. This automatically converts the RF circuit into an analog circuit suitable for analog software.

The application aims to provide an ultra-low voltage constant current source structure, and belongs to the technical field of analog circuits. The structure adopts a differential pair comparator and a depletion NMOS tube N1. The differential pair comparator outputs a control voltage to adjust an output current. PMOS tubes P4 and P5 are low-opening voltage PMOS tubes. The depletion NMOS tube N1 has an opening voltage of -0.3 V, and the lowest working voltage reaches 0.5 V, and the offset effect is small. The traditional operational amplifier constant current source circuit has limitations in a low-voltage environment. The design complexity is simplified, the chip area is reduced, the static power consumption is reduced, and the application is suitable for the power-sensitive field of Internet of Things sensors, medical implant devices and the like. In addition, the ultra-low voltage constant current source structure can realize wide current range output under ultra-low voltage, meet the demand of large current load scene, such as high-brightness LED driving, and expand the application scene.

The invention discloses an inverter power supply fault joint protection circuit. A plurality of MOS tubes (S1, S2, S3 and S4) form a full-bridge conversion circuit, a current sampling resistor (RS1) is connected in series between the MOS tubes S1 and S2, a current sampling resistor (RS2) is connected in series between the MOS tube S2 and an input negative electrode, a current sampling resistor (RS3) is connected in series between the MOS tube S3 and S4, and a current sampling resistor (RS4) is connected in series between the MOS tube S4 and an output negative electrode. According to the invention, in order to realize quick response, signal processing and triggering, analog circuit construction is adopted, and functions of overvoltage and overcurrent flexible setting, sound and light alarm, fault display and the like are realized through software.

This application provides a motor load adaptive adjustment method based on analog circuits, relating to the field of motor control technology, including the following steps: converting the load current in the motor circuit into a first voltage signal, and generating a mode selection signal based on the amplitude and rate of change of the signal; wherein, when the amplitude of the first voltage signal exceeds a first threshold and its rate of change exceeds a second threshold, the mode selection signal indicates a dynamic response mode; otherwise, the mode selection signal indicates a steady-state adjustment mode; when the indication is a steady-state adjustment mode, the first voltage signal is introduced into a first path, which includes a first error amplifier with a first proportional coefficient; when the indication is a dynamic response mode, the first voltage signal is introduced into a second path, which includes a second error amplifier with a second proportional coefficient greater than the first proportional coefficient; generating and outputting a motor drive signal according to the adjustment signal output from the selected path.

The utility model provides an analog unit structure and an analog circuit device. The analog circuit device includes a bottom metal wiring layer including a plurality of tracks and an analog cell including an n-type metal oxide semiconductor (NMOS) active region and a p-type metal oxide semiconductor (PMOS) active region, a plurality of polysilicon layers, and a plurality of metal diffusion layers. In the simulation device, an NMOS (N-channel Metal Oxide Semiconductor) active region, a PMOS (P-channel Metal Oxide Semiconductor) active region, a plurality of polycrystalline silicon layers and a plurality of metal diffusion layers form a CMOS (Complementary Metal Oxide Semiconductor) structure. The apparatus also includes a plurality of guard ring cells surrounding the analog cell and a power rail structure configured to provide a connection between the bottom metal wiring layer and the analog cell.

The invention discloses a vehicle-gauge-level analog circuit performance margin monitoring system and method, the system is based on a vehicle-gauge-level chip comprising a digital circuit and an analog transceiver circuit, and the digital circuit comprises a main controller CPU, a performance analysis engine module and a programmable pressure source module; the main controller CPU comprises a performance reference module and a pressure loopback self-checking module; the method comprises the following steps: in an initialization stage of a vehicle gauge level chip, executing an internal loopback test once under a reference condition, and quantifying a performance reference; in the inter-frame phase of data communication, the programmable pressure source applies instantaneous pressure to the analog transceiver circuit; when pressure is applied, loopback self-inspection is executed, and key performance indexes at the moment are quantified; and the digital circuit compares the performance index under the pressure with a previously stored performance reference, calculates a performance margin, and carries out early warning on an aging state or a potential performance degradation risk of the circuit according to the magnitude and the change trend of the margin.

The invention provides a digital sensor for measuring air pressure parameters. The digital sensor comprises a waterproof sealing gasket, an electric connector, a shell, a wire, a digital circuit board, a hexagonal copper column, an analog circuit board, an adapter, a sensitive element and a connecting nozzle. An anti-aliasing design and a temperature compensation design are adopted on the circuit. The pressure sensor has the advantages of supporting low-voltage power supply, being miniaturized, high in precision, high in reliability, high in environmental adaptability and the like, and lays a technical foundation for subsequent signal acquisition and analysis and localization technical research of the pressure sensor.