765 results about "Analogue circuits" patented technology

A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

The invention provides a PFC (power factor correction) control method with high input power factor and a control circuit thereof. The method comprises the steps of controlling a switching tube to be switched on and switched off according to the principle of leading impulse area to be equivalent, and leading input inductive current and sinusoidal half-wave current to have the equivalent impulse area in each switching period, thereby realizing the high power factor (PF); furthermore, the higher the switching frequency, the closer to 1 the PF value is. In the control circuit, a circuit topological structure of a Boost converter and a control circuit for realizing a variable duty ratio sequence jointly constitute a PFC stage of a commonly used LED (light-emitting diode) driving power supply, the front stage of the PFC stage is connected with the output end of a non-controllable rectifier bridge of a single-phase diode via an input filter capacitor, the back stage of the PFC stage is connected with a DC/DC (direct current/direct current) stage of the commonly used LED driving power supply via an output filter inductor and an output filter capacitor. By adopting the PFC control method, not only the very high input power factor can be realized, but also output voltage ripple can be reduced; furthermore, the control circuit is simple and easy to realize an analog circuit, thereby being conductive to large-scale integration.

The invention relates to a different-dimensional switchable chaotic system design method and a circuit; a four-dimensional hyper-chaos system is constructed by adding variables and feeding back control items based on a three-dimensional generalized Lorenz system family; and a switchable different-dimensional chaotic circuit is designed through a plurality of switch controllers in Multisim software. An analog circuit constructed by the invention is convenient to use and easy to realize by hardware, and has relatively lower cost; the designed switchable circuit not only can flexibly realize the switching between a three-dimensional chaotic system and the four-dimensional hyper-chaos system, but also can return to realize the switch among three chaotic systems in the same dimension; and the systems can serve as practical chaotic modulation and chaotic encryption signals, and can be widely applied to the field of information security cryptography with higher requirements on confidentiality and reliability.

An output circuit, a digital/analog conversion circuit and a display apparatus can reduce the number of required input voltages and the number of transistors to save the necessary area. The output circuit and the digital/analog conversion circuit comprise a selection circuit for receiving as input a plurality of (m) reference voltages having mutually different respective voltage values, selecting two of the voltages according to a selection signal and outputting them and an amplifier circuit for receiving as input the voltages output from the selection circuit at two input terminals T1, T2 and outputting the voltage obtained by interpolating the voltage difference of the two input terminal voltages V(T1), V(T2) to a predetermined ratio. It may alternatively be so arranged that the selection circuit sequentially outputs the selected two voltages and the amplifier circuit sequentially receives as two input the two voltages and outputs the output voltage obtained by interpolation.

The invention discloses an operation method for safely applying a line protection device to a wind power station, which relates to the relay protection of a power plant and is provided aiming at solving the problem that the line protection device in the current system cannot meet the protective requirements of the wind power station very well. The operation method comprises the following steps of: firstly, establishing a real-time simulation model which is a virtual power grid environment, including fault points in a wind power station, a bus and transmission lines, a main transformer unit of a power generator, a current and voltage mutual inductor, an equivalent system and a simulation system; secondly; establishing an experimental detection platform including a real-time digital simulation work station, an RTDS (Real Time Digital System) real-time digital simulator, an analogue quantity output board card, a power amplifier, a line protection device, an analogue circuit breaker, a switch conversion device and a digital quantity input board card; and thirdly, accessing the line protection device to be detected to the power amplifier of the detection system, then connecting the line protection device with the analogue circuit breaker and carrying out various kinds of experiments. The experiment implemented by using the wind power station model and an onsite oscillograph of the wind power station can provide a real and accurate simulation environment so that validation possibility is improved, and therefore the line protection device to be detected can be safely used for the wind power station after detected.

Disclosed is an MCSKPCA based neural network fault diagnosis method for analog circuits, comprising acquiring the output voltage signal of an analog circuit to be diagnosed; performing wavelet transformation on the acquired output voltage signal; calculating the energy eigenvalues of the wavelet coefficients of the output voltage signal, obtained through the wavelet transformation; performing MCSKPCA feature extraction and dimensionality reduction on the energy eigenvalues, and obtaining an optical eigenvector; and sending the optical eigenvector to a BP neural network separator, and outputting a fault diagnosis result by the BP neural network separator. The method can be used for not only diagnosis of linear or nonlinear circuits and systems thereof, but also diagnosis of hard fault and soft fault in the linear or nonlinear circuits.

The invention discloses a spare automatic switching comprehensive tester, and relates to a comprehensive tester of a spare automatic switching device in the field of an electrical power system and a power supply system. The spare automatic switching comprehensive tester can simulate a primary system operation state and a main transformation fault state and implement state detection on a detected spare automatic switching device comprehensively and intuitively on the premise of meeting the requirements of the prior art, and comprises an upper computer, a lower computer, an analogue amplifier, a circuit-breaker analogue circuit and a transformer state simulation circuit. The lower computer is connected with the analogue amplifier through a digital-to-analog converter and is connected with the circuit-breaker analogue circuit and the transformer state simulation circuit; the lower computer and the circuit-breaker analogue circuit are provided with a data interface which exchanges data with the detected spare automatic switching device bidirectionally; the analogue amplifier is provided with a voltage/current output port connected with the detected spare automatic switching device, and output ports P1 and P2 connected with the circuit-breaker analogue circuit; and the transformer state simulation circuit is provided with an interface through which a transformer state signal is transmitted to the detected spare automatic switching device unidirectionally, and output ports B1 and B2 connected with the circuit-breaker analogue circuit.

An analog-circuit fault diagnosis method based on continuous wavelet analysis and an ELM network comprises: data acquisition: performing data sampling on output responses of an analog circuit respectively through Multisim simulation to obtain an output response data set; feature extraction: performing continuous wavelet analysis by taking the output response data set of the circuit as training and testing data sets respectively to obtain a wavelet time-frequency coefficient matrix, dividing the coefficient matrix into eight sub-matrixes of the same size, and performing singular value decomposition on the sub-matrixes to calculate a Tsallis entropy for each sub-matrix to form feature vectors of corresponding faults; and fault classification: submitting the feature vector of each sample to the ELM network to implement accurate and quick fault classification. The method of the invention has a better effect on extracting the circuit fault features and can be used to implement circuit fault classification accurately and efficiently.

A signal generating circuit includes a relaxation oscillator operating to alternately generate a first ramp signal that is periodic at a frequency of the relaxation oscillator and a second ramp signal that is periodic at the frequency of the relaxation oscillator and is out of phase with respect to the first ramp signal The first ramp signal is compared to a first reference voltage and the state of a first flip-flop is changed if the first ramp signal exceeds the first reference voltage. The second ramp signal is compared to the first reference voltage and the state of a second flip-flop is changed if the second ramp signal exceeds the first reference voltage. The first flip-flop is reset in response to a first level of the first ramp signal and the second flip-flop is reset in response to a second level of the second ramp signal. A logical ORing function is performed on an output of the first flip-flop and an output of the second flip-flop to produce an output signal having a frequency that is a multiple of the relaxation oscillator frequency.

An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to (i) measure a width of a symbol in the input signal in response to the plurality of samples and the plurality of phases of the reference clock and (ii) adjust the measured width in response to a correction signal.

The invention relates to a circuit and method for calibrating an on-chip RC time constant by using a switched capacitor, and belongs to the field of analog circuit calibration. The circuit comprises an RC filter on-chip resistor and a variable capacitor; a current mirror, a comparator, a logic control unit, a bias resistor and a switched capacitor circuit. Three PMOS tubes of the current mirror are respectively connected with the bias resistor, the on-chip resistor and one end of the switched capacitor circuit; the drain electrodes of three PMOS tubes of the current mirror are connected with avoltage, the on-chip resistor is connected with the positive input end of the comparator, the switched capacitor circuit is connected with the negative input end of the comparator, and the output endof the comparator is connected with the logic control unit. The logic unit outputs a variable capacitance control code, and the capacitance control code is connected to a variable capacitor to be calibrated; the other ends of the bias resistor, the on-chip resistor and the switched capacitor circuit are all grounded. According to the invention, the influence of parasitic parameters on the calibration precision can be eliminated, the calibration precision is improved to the maximum extent, and the calibration target can be flexibly changed.

The invention discloses an analog circuit fault positioning and parameter recognition method based on a genetic algorithm. Acquiring a transmission function of the measuring point; analyzing fuzzy group information of the analog circuit; the method comprises the following steps: determining a representative fault element of each fuzzy group, when an analog circuit has a fault, firstly obtaining acurrent output, then determining a fault element parameter value vector corresponding to the current output by utilizing a genetic algorithm so as to locate the representative fault element with the fault, and then determining a parameter value range of the representative fault element based on the genetic algorithm. According to the invention, fault diagnosis and fault element parameter recognition of the analog circuit can be effectively realized.

Building blocks for implementing Vector-by-Matrix Multiplication (VMM) are implemented with analog circuitry including non-volatile memory devices (flash transistors) and using in-memory computation. In one example, improved performance and more accurate VMM is achieved in arrays including multi-gate flash transistors when computation uses a control gate or the combination of control gate and word line (instead of using the word line alone). In another example, very fast weight programming of the arrays is achieved using a novel programming protocol. In yet another example, higher density and faster array programming is achieved when the gate(s) responsible for erasing devices, or the source line, are re-routed across different rows, e.g., in a zigzag form. In yet another embodiment a neural network is provided with nonlinear synaptic weights implemented with nonvolatile memory devices.