484 results about "Analogue circuits" patented technology

The invention discloses an early fault diagnosis method for an analog circuit based on subsequence division and Transform. According to the method, an analog circuit time domain response signal is taken as input, a multi-class fault data set constructed by combining PSpice simulation and a Monte Carlo method is divided through a sliding window to generate subsequences, and then local time sequence characteristics are extracted by using depth separable convolution and an SE module and resistance and capacitance fault sensitive frequency bands are adaptively enhanced; the method comprises the following steps: firstly, position coding is carried out on a device, then time sequence information which keeps cross-subsequence with position coding is embedded through token, a Transform encoder modeling global dependency relationship is input, meanwhile, a time sequence coupling effect generated by multi-device collaborative degradation is captured, and finally, multi-class fault diagnosis is completed through a full-connection fault diagnosis module. According to the method, weak fault features and cross-time slice long-range correlation caused by early degradation can be effectively recognized, and experimental results show that the method has high precision and good engineering application value under complex working conditions.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

According to the pure hardware PID current control system and method based on the direct current brushless motor provided by the invention, the negative voltage interference generated by electromagnetic induction is directly filtered in the bus current signal acquisition stage through the cooperation of the current sampling module and the bus negative voltage elimination module; the problem of signal distortion caused by negative voltage in a traditional sampling circuit is eliminated, and the current effective value detection precision is improved; the PID control module constructed based on pure hardware calculates a difference value between a target voltage and an actual voltage in real time through an analog circuit, and generates a proportional, integral and differential composite compensation signal, so that a PWM modulation circuit can adjust duty ratio output in real time according to the compensation signal, and it is ensured that a bus current of a motor driver is rapidly converged to a target value; the whole scheme does not need to depend on a microcontroller and a complex software algorithm, closed-loop current control is achieved through discrete devices, and the system cost is reduced.

The invention discloses a crystal oscillator circuit fault classification technology based on a multi-source information fusion network, and belongs to the technical field of analog circuit fault diagnosis. Firstly, a multi-source data set of different measurement points of the crystal oscillator circuit is acquired; carrying out conversion from a time domain to a frequency domain on the data set by utilizing fast Fourier transform; extracting data fault features by using a convolutional neural network, and performing a trust distribution function under each piece of source data by using a softmax classifier; fusing different trust distribution functions under the multi-source data by adopting a D-S evidence theory to obtain a final diagnosis result and diagnosis probability output, and calculating cross entropy loss; and finally, training model parameters through back propagation to obtain a final diagnosis model. According to the method, the time-frequency transformation algorithm, the deep neural network algorithm and the information fusion algorithm are combined, a multi-source information fusion network is constructed, the defects of an existing diagnosis model in crystal oscillator circuit fault classification are overcome, and the accuracy and stability of crystal oscillator circuit fault diagnosis are remarkably improved.

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

The invention aims to provide the analog circuit frequency response flatness digital compensation calibration method which can reduce the hardware device requirement, the production process requirement and the production cost and meet the frequency response flatness requirement of low-frequency alternating current test equipment. The method comprises the following specific steps: S1, setting a frequency band range and extracting a plurality of groups of original data; s2, setting a sampling rate and an order; s3, generating a target frequency range, and setting a plurality of target frequency points; s4, extrapolating a frequency response curve and obtaining a frequency response value of a specific frequency; step S5, calculating frequency response characteristics according to the original data extracted in the step S1, and performing frequency response interpolation calculation of a plurality of target frequency points in a target frequency range based on a linear difference method to obtain a frequency response curve; s6, carrying out reciprocal processing on the frequency response curve to obtain a compensation curve; and S7, calculating calibration parameters according to the compensation curve. The method is applied to the technical field of electric signal processing.

A method, system, and apparatus for determining a yield estimate for an integrated circuit are provided. The method includes the acts of generating a set of vectors of scaled parameter values, simulating an output of the circuit to identify a subset of the set of vectors, identifying a set of points on boundaries of failure regions in the parameter space, generating a set of sample points for each failure region. and determining a yield estimate based on the sets of sample points

The invention discloses a low-power-consumption dynamic voltage control method and a low-power-consumption dynamic voltage control circuit, the low-power-consumption dynamic voltage control circuit comprises an analog circuit module and a digital circuit module which are arranged in a top module unit of a chip, and the analog circuit module comprises an OSC clock generation circuit which is used for generating a clock required by the digital circuit module. And the digital circuit module digit comprises a low-power-consumption dynamic voltage control circuit. According to the invention, the function of high-dynamic real-time adjustment of the voltage control code with extremely low power consumption is realized through pre-opening and pre-closing of the clock.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an apparatus is provided for adaptive signal conditioning for biopotential acquisition. The apparatus includes an analog circuit configured to amplify biopotential signals, and a mixed-signal circuit (e.g., which can include an adaptive digital algorithm) coupled to the analog circuit and configured to suppress aggressor signals such as baseline wandering signals and power-line-induced noise in the biopotential signals before amplification of the biopotential signals.

The invention discloses a low-cost soft error reinforcement method based on an approximate triple modular redundancy unit. The method comprises the following steps: establishing an approximate library: establishing an approximate gate unit for a basic gate unit of a to-be-reinforced circuit, and integrally establishing an approximate gate unit library; software modeling: acquiring basic information of each standard gate unit in the circuit, and evaluating the performance of the circuit according to a soft error propagation physical model so as to perform software modeling; and approximate reinforcement: selecting a gate unit in a to-be-reinforced circuit in a semi-directional manner based on improved dynamic adjustment NSGA-II to replace the gate unit with an approximate gate unit in an approximate library, simulating circuit performance indexes through an estimator, performing multi-target optimization solution, obtaining an optimal compromise of area, power consumption and soft error rate through iteration, and giving an approximate reinforcement scheme. The method has high efficiency, practicability and universality, can be used for guiding low-cost soft-error-tolerant approximate reinforcement of various high-reliability structures such as triple modular redundancy (TMR) and the like, and can adapt to multi-scene and multi-requirement circuit reinforcement design.

The embodiment of the invention provides a spurious emission elimination circuit, a spurious emission elimination method and electronic equipment. The spurious emission elimination circuit comprises a signal transmission branch and at least one spurious emission simulation circuit, the signal transmission branch is used for receiving the input signal and the at least one target stray analog signal, and performing stray elimination on the input signal based on the at least one target stray analog signal to obtain an output signal; the stray simulation circuit is used for receiving corresponding stray simulation information and output signals; generating an initial spurious simulation signal based on the spurious simulation information; and performing phase correction on the initial spurious analog signal based on the output signal to generate a target spurious analog signal.

The invention belongs to the technical field of stability compensation circuits, and particularly relates to a stability compensation circuit structure of a high-speed operational amplifier, which is characterized by comprising a function module, a first control module, a second control module, a third control module, a fourth control module and a fourth control module, and the function module comprises an input stage, a differential common-base gain stage, a common-base level converter module and an output stage, and the stability compensation assembly comprises a dual-frequency load unit which is matched with the functional module and comprises a low-frequency load branch and a high-frequency load branch which are connected in parallel. Through the synergistic effect of the double-frequency load unit and the pole regulation and control capacitor, gain segmentation regulation and control of low-frequency high gain and high-frequency fast attenuation are achieved, the open-loop gain of the operational amplifier breaks through the limitation of 30dB of an existing HBT single-stage operational amplifier, and meanwhile the problem that high-frequency phase shift changes too fast is effectively restrained; through simulation verification, the phase margin can reach 67 degrees, the stability requirement of 45-60 degrees and above of an analog circuit is met, and the core contradiction that the high-gain bandwidth and the phase margin of an HBT device are difficult to balance is thoroughly overcome.

The embodiment of the invention provides a method, device and equipment for simulating circuit layout design, a medium and a program product, and relates to the field of chip design tools. The method includes determining layout design constraints associated with a plurality of device groups in a circuit design based on circuit design data, and generating a plurality of layout cell groups based on the layout design constraints, each layout cell group having an internal layout and an internal connection. The method further includes generating a layout by modifying at least one of a position and a shape of the plurality of layout cell groups based on the layout design constraints, determining a global layout of the plurality of layout cell groups, and determining wiring based on the layout design constraints. In this way, the layout design constraint can be automatically determined from the analog circuit design data, and then the layout unit group, layout and wiring are automatically generated in combination with the layout design constraint, so that end-to-end automatic generation of the analog circuit layout is realized.

The invention discloses a phase synchronization circuit, an expanded phase-locked loop circuit and a delay phase-locked loop circuit. The phase synchronization circuit comprises a clock comparison unit, a biasing circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter and a clock output unit. The clock comparison unit is connected with the clock output unit, the charge pump circuit and the time / analog conversion circuit; the biasing circuit is connected with the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected with the compensation charge pump circuit; the loop filter is connected with the charge pump circuit, the compensation charge pump circuit and the clock output unit. According to the phase synchronization circuit and the expansion structure thereof, time information can be directly converted into voltage for leakage current compensation, so that comparison action based on the voltage is not needed, and analog circuits such as an integrated operational amplifier and a voltage comparator are not needed. Therefore, it is possible to suppress an increase in the chip area of the compensation circuit and to reduce the phase error of the output clock.

The invention discloses a PMUT array ultrasonic transceiver circuit system, and relates to the technical field of electronic circuits and systems, and the system comprises a GPU processing module, an FPGA main control module and an ultrasonic analog circuit. The GPU processing module generates an optimal array element gating matrix by using an array element gating matrix generation model; the FPGA main control module drives the ultrasonic analog circuit to perform time-sharing gating on the transmitting array element and the receiving array element according to the optimal array element gating matrix; performing phase control excitation on the transmitting array element when the transmitting array element is gated; performing beam forming on the processed ultrasonic echo signal when the receiving array element is gated; the ultrasonic analog circuit performs time-sharing gating on the transmitting array element and the receiving array element, and generates a high-voltage pulse when the transmitting array element is gated; ultrasonic echo signals are collected and processed when the receiving array elements are gated; and the GPU processing module performs three-dimensional image reconstruction according to the synthesized ultrasonic echo signal to obtain a three-dimensional ultrasonic image. According to the invention, the imaging speed and resolution are improved.

The present invention discloses a Unified Deep-Learning Neural Network (U-DNN) Architecture capable of modeling a wide range of AMS circuits effectively and shows the ways it can be used for on demand circuit specification, design optimization and self-adaptation. Applying the U-DNN architecture for analog circuit characterization demonstrated consistent performance across all the DUTs, with an R2Score exceeding 0.95 with {μE,σE}<1% for the test split data, validating its accuracy. The U-DNN architecture exhibited an average MaPE of less than 1% over unseen test cases, showcasing its strong generalization capabilities. Remarkably, the knowledge encapsulated in the U-DNN architecture, gained from modeling diverse AMS circuits in CMOS 180 nm and 65 nm technologies, translated into accurate modeling of AMS circuits in CMOS 28 nm. The U-DNN architecture serves as a versatile platform for modeling various AMS circuits for different applications, reducing the extensive design exploration time needed to select appropriate NN structures.

The invention discloses an inverter arc discharge current detection method based on data enhancement. The method comprises the following steps: acquiring a first current signal of an inverter in a normal working state; an analog circuit is constructed with the same circuit topology as the inverter, the inverter is replaced with a load in the analog circuit, and a second current signal is generated in the analog circuit through an arc discharge generator; superposing the first current signal and the second current signal to obtain an approximate arc discharge current signal; and performing data expansion and noise addition processing on the approximate arc discharge current signal to obtain enhanced negative example data. When a new inverter product is researched and developed, current data of normal work of the product only need to be collected again, then arc discharge current data of the product can be obtained according to the steps (data superposition and noise adding processing), and a large amount of arc discharge current data do not need to be collected again.

The invention provides a circuit design-process collaborative optimization method, a preparation method and a circuit based on an edge contact two-dimensional transistor, and aims at remarkably improving the load linearity, the output resistance and the switching stability of the two-dimensional transistor by adopting an edge contact process and optimizing the geometric parameters of the transistor according to the performance requirements of an analog circuit. The method specifically comprises the optimization design of the edge contact transistor, the characterization and improvement method of the load performance, and the system integration and application of the edge contact transistor in a high-performance analog circuit module. The invention provides a complete solution from transistor-level process optimization to circuit-level performance improvement, and provides a key technical path for design and manufacturing of high-linearity and high-stability analog and mixed signal integrated circuits based on novel two-dimensional semiconductors.

This application relates to the field of integrated circuit automated design technology, and particularly to a method, apparatus, and electronic device for optimizing transistor layout in analog circuits. The method includes: acquiring a device group layout diagram of transistors in an analog circuit; encoding the device group layout diagram into a character array; generating an initial parent population based on the character array; determining the genotype of the initial parent population for evolutionary iteration based on the character array; iterating the initial parent population based on its genotype, performing multi-objective evaluation on the current parent population based on offspring individuals during each iteration, until a preset number of iterations is reached; the current parent population includes one of the initial parent population and one of the evolved parent populations; and determining the optimization result of the device group layout diagram based on the last evolved parent population. This solves the problem in related technologies where transistor layout in analog circuits is difficult to balance device electrical matching performance with layout area and wiring complexity.

The invention discloses an ultralow-temperature quantum controller applied to a low-temperature superconducting quantum computer, which comprises an analog circuit part and a digital circuit part, and is characterized in that the analog circuit part comprises two XY channels and three Z channels, each XY channel comprises two signal paths and an on-chip balun; each signal path comprises a nonlinear digital-to-analog converter NLDAC, an intermediate-frequency filter, an adjustable gain amplifier VGA, a quadrature mixer and a quadrature local oscillator signal generator, the input end of the quadrature mixer is connected with the output end of the quadrature local oscillator signal generator, and the output ends of the two signal paths of the XY channel generate XY channel control signals of the XY channel through on-chip balun combination. Each of the three Z channels includes three independent, independently adjustable digital-to-analog converters (DACs) for generating Z channel control signals for the three Z channels. The invention aims to shorten the distance between the controller and the quantum chip, improve the fidelity of the quantum computer and reduce the expense of quantum error correction.

The application discloses a kind of analog circuit fault diagnosis method based on wavelet scattering and ensemble learning, to solve the problem that analog circuit fault response aliasing leads to difficult fault diagnosis.First, the circuit response is divided into multiple frequency band subsets by wavelet scattering transform, and the fault features of the subsets are enhanced using Fisher discriminant analysis.Second, each frequency band subset is sent to different extreme learning machines under Bagging integration, and the classification accuracy of each fault mode in the frequency band subset is used as the class weight of the extreme learning machine.Then, the output values of each extreme learning machine are weighted to obtain the fused output result, and the fault class is determined accordingly.Finally, two example circuits are simulated, and the simulation results show that the diagnostic accuracy is 100%, indicating that the method is feasible and effective, and can realize fault classification and positioning.

The invention provides a multi-agent reinforcement learning optimization method of an analog circuit and a related device. The method comprises the following steps: setting an ideal performance parameter group of the analog circuit; clustering the components according to the transient current curves of the components to obtain a plurality of component groups; configuring an intelligent agent for each component group, and enabling the intelligent agent to output a circuit parameter value according to the ideal performance parameter group; applying the circuit parameter value to a simulation circuit for simulation to obtain a simulation circuit performance value; updating the intelligent agent according to the simulation circuit performance value and a preset target performance value to obtain a target intelligent agent; the elements are clustered by analyzing the actual current characteristics of the circuit under transient response, so that the elements with similar functions are divided to the same agent, thereby breaking the limitation of a physical module, realizing parameter decoupling and collaborative optimization, and improving the convergence efficiency.

The invention discloses a heuristic-based iterative legalization method and system for an analog circuit layout, and the method comprises the steps: dividing layout groups according to a special structure and an array module in a layout based on the initial layout of the layout containing overlapped devices or modules; constructing a constraint graph for describing the relative position relationship between the layout groups, and solving symmetric constraint conflicts in the layout so as to ensure that all symmetric constraints are met; performing simulation processing on a non-overlapping constraint, a minimum area constraint and a minimum spacing constraint through a code simulation solver to generate an initial legal layout; and iteratively adjusting the constraint graph based on a heuristic method, identifying a suspicious group and adjusting the constraint edge of the suspicious group, and re-verifying and repairing the symmetric constraint after each adjustment until the layout area converges. According to the method, the symmetric constraint is synchronously verified and repaired in each iterative optimization, so that the layout area is minimized on the premise of ensuring the layout legality, and the solving efficiency is greatly improved at the same time.

The invention discloses a PWM signal generation method, module and related device, and the method comprises the steps: sampling a comparison signal based on a sampling period, judging the size relation between the actual current and instruction current of a motor based on the comparison signal, selecting an upper switch tube of a driver or a lower switch tube of the driver based on a judgment result, and generating a PWM signal according to the upper switch tube or the lower switch tube. And judging whether the turn-on time of the selected switch tube reaches the minimum turn-on time, if so, generating an upper tube control signal and / or a lower tube control signal based on the judgment result, and if not, re-sampling the comparison signal based on the sampling period. According to the PWM signal generation method and module and the related device, only the actual current needs to be compared with the instruction current, and the analog circuit calibration difficulty is smaller. In addition, judgment on the turn-on time and the dead time of the switching tube is introduced, and the use safety of a switching device can be considered.

The application relates to the fields of signal processing, image processing and communication engineering, and particularly relates to a real-time sparse signal reconstruction method based on an analog circuit, which comprises the following steps: acquiring an observation signal and an observation matrix; based on the observation signal and the observation matrix, an analog circuit is constructed; the numerical value of the observation signal is converted into a corresponding electric signal and applied to the input end of the analog circuit; the analog circuit is powered on and operated to a steady state, the steady-state voltage values of a plurality of predetermined nodes in the analog circuit are measured, and the measured steady-state voltage values are output as the reconstruction values of the sparse signal. The application adopts a technical path of a full-analog computing system architecture, and aims at a sparse signal reconstruction problem, converts a key mathematical model (specifically, an equation group represented by KKT conditions) in a solving process of the problem into a circuit physical structure, and outputs an optimal solution through a steady-state response of the circuit in one step.

This invention discloses a method, apparatus, medium, and device for parameter optimization of analog circuits, relating to the field of analog circuit technology. The invention automatically identifies current paths through a search algorithm to deeply analyze the circuit topology, determine the symmetry structure in the analog circuit, and constructs symmetry constraints based on the identical optimization parameters of electrical components within the symmetry structure. Simultaneously, it transforms the product of the transistor's gate width and the number of parallel connections into the total width and sets the optimization boundary. This combination reduces the dimensionality of the optimization variables while ensuring that the parameter optimization process conforms to the layout design of the analog circuit. Furthermore, it combines a population mutation algorithm and a non-dominated sorting genetic algorithm with an elitist strategy to perform iterative optimization within the constructed efficient search space, significantly improving the convergence speed of analog circuit parameter optimization, reducing computational costs, and enhancing the practicality of the analog circuit parameter optimization method.

The invention relates to a sensing and control device (40) and method for a weight measuring device (30) comprising a loading unit for loading material to be weighed. In order to be able to measure accurately with less expensive components, the sensing and control device comprises an analog circuit (50) and a control circuit (60). The analog circuit (50) is configured to receive a weight measuring signal, to convert the received weight measuring signal into a first voltage signal, to subtract a second voltage signal from the first voltage signal when the loading unit is loaded with material to be weighed to generate a third voltage signal representing the weight of the material to be weighed, the second voltage signal representing the weight of at least the loading unit not loaded with material to be weighed. The control circuit (60) is configured to receive the first voltage signal when the loading unit is not loaded with material to be weighed, to convert the first voltage signal into a first digital signal, and to generate a pulse width modulation, PWM, signal having a pulse width, the pulse width representing the weight measured by the weight measuring device when the loading unit is not loaded with material to be weighed, and the control circuit is further configured to convert the third voltage signal into a second digital signal representing a weight measurement of the material to be weighed. The analog circuit (50) is configured to generate the second voltage signal from the PWM signal generated by the control circuit, wherein the voltage level of the second voltage signal is proportional to the pulse width of the PWM signal.

There is provided an analog circuit comprising: a plurality of analog functions, which are divided into at least two groups of analog functions, and an interconnection structure configured to interconnect the plurality of analog functions so as to enable transfer of both voltage and current signals between analog functions among the plurality of analog functions. The interconnection structure comprises at least two hierarchy levels of interconnections, wherein a local-bus hierarchy level is configured to interconnect analog functions of a respective group, and a global-bus hierarchy level is configured to interconnect analog functions of the plurality of groups. The local-bus hierarchy level comprises voltage signal lines for transferring voltage signals and / or current signal lines for transferring current signals, and the global-bus hierarchy level comprises voltage signal lines for transferring voltage signals and / or current signal lines for transferring current signals.

The application provides a rail transit vehicle electrical cabinet maintenance practical training device, which comprises an upper computer and a plurality of simulation relays; the upper computer is used for generating a control instruction according to a maintenance practical training requirement and sending the control instruction to the plurality of simulation relays; the simulation relay comprises a controller and at least one contact simulation circuit; the conduction or cutoff of the contact simulation circuit is determined based on the output level of the output pin controlled by the controller; the simulation relay is used for analyzing the received control instruction based on the controller and controlling the output pin to output a high level or a low level based on the analysis result to control the conduction or cutoff state of the contact simulation circuit and simulate the maintenance practical training requirement. By adopting the controller plus the contact simulation circuit to construct the simulation relay, various fault states can be flexibly injected, and the safety and efficiency of the practical training are greatly improved.