1171 results about "Analogue circuits" patented technology

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

A high-energy efficiency, low-power consumption passive radio frequency identification tag chip. A high-energy efficiency bridge rectifier circuit is constructed in an analog circuit portion by using an NMOS transistor, and an alternating-current voltage signal is converted into a direct-current signal. Meanwhile, a three-stage amplitude-limiting circuit is added to prevent an induced voltage from being too large and thus breaking down a transistor. The load at two ends of an antenna is changed by using an encoded signal to control the MOS transistor turning on and off, and then voltage values at the two ends of the antenna are adjusted by controlling a leakage current, achieving the purposes of load modulation and signal transmission. High-precision, high-speed decoding is achieved at a digital circuit portion by using a pulse position modulation decoder. The encoded signal is generated by using a Manchester encoder based on FSM control. An anti-collision circuit is used to handle a possible situation in which a plurality of RFID tags simultaneously exist in an interrogation zone. A uniquely designed read timing control circuit is used in an EEPROM memory portion, so that the power consumption of the circuit may be effectively reduced. The described chip has the characteristics of high energy efficiency, low power consumption, and low adjustment index, and is widely applied to the field of RFID identification.

The invention discloses a process deviation-oriented analog circuit parameter optimization method, which comprises the following steps of: S1, carrying out multi-objective optimization on a given analog circuit under a nominal process condition, identifying and eliminating a design region with poor performance according to an optimization result, and carrying out clustering analysis to obtain an optimal design region; dividing the remaining high-quality areas into a plurality of initial trust areas; s2, modeling the finite Monte Carlo simulation data in the initial trust area by using a heterovariance Gaussian process model, capturing an average level and a change trend of circuit performance, and predicting behaviors of the circuit under process change; and S3, the required yield is kept while the performance is optimized, probability assurance is provided for the performance value by adopting the risk value, and a design point optimization set and a corresponding Pareto optimal solution set are finally obtained through multiple iterations in the optimization stage of considering the process change. According to the method, the high-quality Pareto optimal solution set meeting the yield constraint is found under the process change of unknown distribution, and the size of an analog circuit is optimized.

A mixed-signal circuit may include an analog circuit and a digital circuit coupled to the analog circuit, wherein the analog circuit is configured to, in a normal operation mode, provide an analog signal to the digital circuit, and wherein the digital circuit is configured to, in the normal operation mode, provide a digital signal to the analog circuit, the mixed-signal circuit may further include a test signal generator configured to, during a test operation mode, receive the digital signal from the digital circuit, generate a test signal based on the digital signal, and provide the test signal to the digital circuit, wherein the test signal generator is configured to generate the test signal using an emulation of the analog circuit, and wherein the mixed-signal circuit is tested based on an output of the digital circuit that is generated in response to the test signal.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

The invention discloses an early fault diagnosis method for an analog circuit based on subsequence division and Transform. According to the method, an analog circuit time domain response signal is taken as input, a multi-class fault data set constructed by combining PSpice simulation and a Monte Carlo method is divided through a sliding window to generate subsequences, and then local time sequence characteristics are extracted by using depth separable convolution and an SE module and resistance and capacitance fault sensitive frequency bands are adaptively enhanced; the method comprises the following steps: firstly, position coding is carried out on a device, then time sequence information which keeps cross-subsequence with position coding is embedded through token, a Transform encoder modeling global dependency relationship is input, meanwhile, a time sequence coupling effect generated by multi-device collaborative degradation is captured, and finally, multi-class fault diagnosis is completed through a full-connection fault diagnosis module. According to the method, weak fault features and cross-time slice long-range correlation caused by early degradation can be effectively recognized, and experimental results show that the method has high precision and good engineering application value under complex working conditions.

Disclosed in the present application are an analog circuit netlist division method and system based on reinforcement learning. The method comprises: acquiring an analog circuit netlist; performing feature extraction processing on the analog circuit netlist, so as to obtain circuit features; performing classification processing on the circuit features on the basis of a hierarchical reinforcement learning algorithm, so as to obtain a classification result; and performing function labeling processing on the classification result, so as to obtain a modular circuit netlist. By means of the present application, automatic identification and classification can be performed on an analog circuit in combination with machine learning, so as to better adapt to different types of circuits and problems, thereby improving the quality and efficiency of division. The present application can be widely applied to the technical field of circuit division.

The invention aims to provide a method and a system for realizing a built-in self-test code of a PCIE (Peripheral Component Interface Express) physical layer. The method comprises the following steps of: integrating PCIE BIST GEN module packaging data in a controller layer and sending the data to a physical coding sub-layer; the physical coding sub-layer codes the packaged data and sends the coded data to the physical medium adaptation layer; and the physical medium adaptation layer converts the coded data into serial data and transmits the serial data back to the controller layer. According to the invention, the BIST test assembly meeting the PIPE protocol requirement is embedded in the PCS layer, and compared with a traditional BIST test scheme, through early-stage simulation and post-silicon test data result analysis, not only can the electrical performance test requirement of an original analog circuit be met, but also the test coverage of the PCS layer is increased. And the full-stack coverage test from the physical signal to the protocol logic is realized.

The invention belongs to the technical field of integrated circuits, and particularly relates to an analog circuit yield optimization method under multiple environment angles based on a Bayesian neural network. According to the method, a Bayesian neural network (BNN) is used for carrying out synchronous modeling on yield and nominal performance under multiple environment angles, and yield optimization under the multiple environment angles is executed by embedding the BNN into a Bayesian optimization framework. The BNN model provided by the invention can better learn the correlation between the yield and the performance under different environmental angles, provides a strong modeling capability for the yield and the uncertainty thereof, and improves the yield optimization efficiency. Compared with other baseline methods, under the condition that the same target yield is achieved, the circuit simulation time cost can be saved by 45.3%, under the same circuit simulation time cost, a design point with the higher yield can be obtained, and the yield is improved by 3.2%.

The invention relates to a capacitor mismatch foreground calibration method suitable for an SARADC, and the method comprises the steps: S1, enabling an analog input signal, a random jitter signal and a dynamic element to be matched with each other, and jointly inputting the signals into a capacitive digital-to-analog converter; s2, comparing the output of the capacitive digital-to-analog converter with a reference point through a comparator, and storing to obtain an output digital code; s3, calculating an evaluation value of the corresponding output digital code; s4, obtaining an error between the actual output value and the reference output value estimation value; s5, iterating the capacitance weight and the random signal according to the size of the error by utilizing an LMS (Least Mean Square) algorithm; and S6, continuously changing the capacitance weight and the random signal to enable the error to be within an allowable range, and obtaining more accurate output. According to the invention, no additional analog circuit needs to be added for capacitor mismatch calibration, and parameters such as the significant bit number and the spurious-free dynamic range of the ADC are obviously improved.

A method is provided for transmitting transmission data from a sensor controller that detects a pen to the pen through a sensor electrode group. The pen includes a pen tip electrode arranged near a pen tip, and an analog circuit that detects edges of a signal led to the pen tip electrode. The pen also includes a digital circuit that performs a correlation operation of an output signal of the analog circuit and known patterns to detect the transmission data. The sensor controller is configured to generate a pulse signal representing the transmission data. The sensor controller is configured to transmit the pulse signal, by using a main signal and a sub signal of the pulse signal so as to enhance the edges, thereby transmitting the transmission data through the sensor electrode group.

The invention discloses an analog IC netlist layout collaborative optimization method and system based on a reinforcement learning algorithm, and the method comprises the steps: generating an initial netlist of an analog IC, and inputting the initial netlist into a pre-built simulation platform; generating an analog IC circuit layout according to the initial netlist of the analog IC, and performing simulation through a simulation platform; the reinforcement learning agent builds a graph neural network to execute an optimization task based on a pre-built analog IC netlist multilateral heterogeneous graph, generates an optimized analog IC netlist and sends the optimized analog IC netlist to the simulation platform; a new analog IC circuit layout is generated according to the optimized netlist of the analog IC, the simulation platform simulates the optimized netlist of the analog IC and the new analog IC circuit layout, and the analog IC circuit layout is further optimized through a reinforcement learning agent; and continuously interactively optimizing the reinforcement learning agent and the simulation platform until a final parameter combination meeting the performance index is obtained. According to the invention, the efficiency and performance of circuit optimization are greatly improved.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

Disclosed are a quick simulation and optimization method and system for analog circuits. Aiming at a problem that a customized circuit model is difficultly modeled in a design process of the analog circuit, and the problem of a low circuit design efficiency caused by a slow electromagnetic field simulation speed, the invention proposes to firstly construct a device library, build a circuit and interconnect an AI network to obtain a comprehensive network parameter of the AI network; the comprehensive network parameter in a simulation process is compared with a network parameter target of an analog circuit, and an circuit layout of the analog circuit corresponding to the AI network is output to a three-dimensional full-wave electromagnetic field simulation tool for simulation and verification when requirements are met.

The invention provides a digital-analog hybrid simulation method and device.The method comprises the steps that a simulation modeling file is generated according to design information of an analog circuit of a chip, and the simulation modeling file comprises a digital netlist, device library configuration, device mapping configuration, simulation control parameters, simulation signal variables and digital-analog interface conversion rules; and performing digital circuit simulation according to the design information of the digital circuit of the chip and the simulation modeling file, and generating a digital-analog hybrid simulation result of the chip. According to the method provided by the invention, the compatibility between digital-analog hybrid simulation tools can be improved.

According to the pure hardware PID current control system and method based on the direct current brushless motor provided by the invention, the negative voltage interference generated by electromagnetic induction is directly filtered in the bus current signal acquisition stage through the cooperation of the current sampling module and the bus negative voltage elimination module; the problem of signal distortion caused by negative voltage in a traditional sampling circuit is eliminated, and the current effective value detection precision is improved; the PID control module constructed based on pure hardware calculates a difference value between a target voltage and an actual voltage in real time through an analog circuit, and generates a proportional, integral and differential composite compensation signal, so that a PWM modulation circuit can adjust duty ratio output in real time according to the compensation signal, and it is ensured that a bus current of a motor driver is rapidly converged to a target value; the whole scheme does not need to depend on a microcontroller and a complex software algorithm, closed-loop current control is achieved through discrete devices, and the system cost is reduced.

The invention discloses a parameter determination method and device of an analog circuit, a medium and a product, and relates to the technical field of integrated circuit design. Local performance feedback and global topology perception of performance index parameters are used as input parameters, and pertinence and generalization ability of parameter adjustment are remarkably improved. Through a strategy function, a parameter candidate set of a target analog circuit is obtained, through multi-group sampling processing, variance of strategy gradient estimation is reduced, and training stability and convergence speed are improved. Depending on a value network is not needed, and training resource overhead is reduced. And applying the parameter candidate set output by the strategy function to the simulation processing scene to realize the accuracy of simulation processing evaluation. The target performance indexes are extracted from the simulation result, optimization of the performance indexes is achieved, the multiple target performance indexes are processed according to the multi-target reward function, balance selection and rejection are achieved in the multiple performance indexes, the parameter combination corresponding to the highest advantage value is obtained, and the reliability of the analog circuit parameter determination process is improved.

The invention provides a constant-power load analog circuit, a constant-power adjusting method and a rack-mounted load box, and belongs to the field of rack-mounted load boxs.The analog circuit comprises a rectifying circuit, a diverter, a power module, a fan module and a control and drive circuit, and the power module comprises at least one heating tube and at least one transistor. The control and drive circuit comprises a main control circuit, a voltage signal processing circuit, a current signal processing circuit, a power setting and display module and at least one IGBT drive circuit, the base electrode of the transistor is connected to the main control circuit through the IGBT drive circuit, and the power setting and display module is connected to the main control circuit and used for inputting a set power value. The main control circuit collects voltage and current of an external power supply, calculates a rated power value, calculates a signal duty ratio according to a set power value and the rated power value, outputs a PWM wave, controls on or off of a transistor through the IGBT driving circuit, dynamically adjusts actual output power of the load simulation circuit to be consistent with the set power value, and controls the load simulation circuit to work. And the power regulation precision of the load box is improved.

The invention discloses a crystal oscillator circuit fault classification technology based on a multi-source information fusion network, and belongs to the technical field of analog circuit fault diagnosis. Firstly, a multi-source data set of different measurement points of the crystal oscillator circuit is acquired; carrying out conversion from a time domain to a frequency domain on the data set by utilizing fast Fourier transform; extracting data fault features by using a convolutional neural network, and performing a trust distribution function under each piece of source data by using a softmax classifier; fusing different trust distribution functions under the multi-source data by adopting a D-S evidence theory to obtain a final diagnosis result and diagnosis probability output, and calculating cross entropy loss; and finally, training model parameters through back propagation to obtain a final diagnosis model. According to the method, the time-frequency transformation algorithm, the deep neural network algorithm and the information fusion algorithm are combined, a multi-source information fusion network is constructed, the defects of an existing diagnosis model in crystal oscillator circuit fault classification are overcome, and the accuracy and stability of crystal oscillator circuit fault diagnosis are remarkably improved.

The invention discloses a personal dosimeter capable of nuclide identification, and the dosimeter comprises a scintillation detector which is composed of a scintillation crystal and SiPM and captures an energy spectrum signal of a ray; the signal amplifier receives the voltage signal output by the SiPM and preprocesses and amplifies the voltage signal; the multichannel analyzer is used for receiving the amplified signal output by the signal amplifier and realizing energy spectrum acquisition in a target energy range; and the MCU receives the signals acquired by the multichannel analyzer and performs energy spectrum analysis. According to the invention, the scintillation detector based on SiPM and scintillation crystals is used, so that the small size and high sensitivity of the personal dosimeter are realized; according to the multi-channel analyzer, the multi-channel analyzer capable of setting the energy range is realized through the ADC and the comparator, and the design of a peripheral circuit is extremely simplified; the simplified nuclide identification method is designed based on prior information, the range of a nuclide library is narrowed, and the requirements of nuclide identification in a specified application scene for the computing power of a system and the complexity of an analog circuit are further reduced.

An acoustic device includes circuit elements, such as analog circuit components, between the first and second substrate and coupled to an acoustic resonator to form an acoustic filter within the acoustic device. In some examples, forming the circuit elements between the first substrate and the second substrate includes forming the first circuit elements in insulating material on the second substrate before coupling the second substrate to a first side of the first substrate. The circuit elements disposed between the first and second substrates may include capacitors, inductors, and electrical interconnects coupled to the acoustic resonator on the first substrate. Additional features may be included in the insulating material. The acoustic device avoids the need for bulky analog components coupled to the acoustic resonator via long interconnects through a package substrate, making it possible to reduce an acoustic device's package size.

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

The invention relates to a virtual simulation and debugging system for a medical heavy ion cancer treatment accelerator. The system comprises a server and a client, the server comprises an industrial control server, a webpage server and a database server, and the industrial control server performs data interaction with the client through the webpage server; a virtual system and an analog circuit system are arranged in the industrial control server; the virtual system and the analog circuit system are set based on equipment of a real medical heavy ion cancer treatment accelerator, and the virtual system and the analog circuit system simulate and debug simulation equipment and debugging equipment of the medical heavy ion cancer treatment accelerator according to preset parameters. The webpage server publishes all simulation and debugging data into a webpage for a client to call, and the database server is used for storing preset data, data generated by debugging and simulation of the virtual system and the simulation circuit system and debugging preset rule data. The real equipment is prevented from being damaged, and the running time of the real accelerator can also be prevented from being wasted.

The invention discloses a parallel-serial conversion circuit based on a composite dielectric gate photosensitive detector, and belongs to the field of integrated circuits. The parallel-serial conversion circuit comprises a composite dielectric gate photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a pre-charging circuit, a comparator, a counter, 8-256 decoders, a first AND gate, 256 second AND gates and a 256 input OR gate. According to the parallel-serial conversion circuit, all digital circuit parts are converted into analog circuits, so that the circuit design complexity is reduced, the circuit simulation and layout design iteration period is shortened, the power consumption and the area of a chip are effectively reduced, and the design of a subsequent miniaturized system is facilitated.

The invention provides a parallel-serial conversion circuit and method based on clock edge alignment, and the circuit comprises a clock jump delay circuit which is used for carrying out the phase delay of an input signal of an analog circuit, a frequency division module which is used for carrying out the frequency division processing of the signal after phase delay, and a clock edge alignment module. The input signal is directly subjected to frequency division processing and then is sent to the digital circuit; the clock synchronization detection circuit is used for carrying out synchronization detection on the signal after phase delay and frequency division processing and the signal output by the digital circuit; the logic control module is used for sending a control signal to the clock hopping delay circuit according to a synchronous detection result; the clock hopping delay circuit adjusts the phase of the analog clock according to the control signal until synchronous detection results are consistent, and clock edge alignment of the analog circuit and the digital circuit is completed; and performing data parallel-serial conversion according to the analog circuit and the digital circuit after the clock edges are aligned. According to the invention, clock alignment can be automatically realized.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

The invention discloses a clock synchronization method and system based on an FPGA, and the method comprises the steps: obtaining the frequency of a synchronization signal and the period of a local clock signal, carrying out the first frequency division processing of the local clock signal through the first internal logic of the FPGA, and obtaining a first clock signal; calculating a phase difference and a frequency difference between the first clock signal and the synchronizing signal through a second internal logic of the FPGA; and according to the frequency difference and the phase difference, synchronous locking of the local clock signal and the synchronous signal is realized through the first internal logic and the second internal logic of the FPGA, and the synchronized clock signal is output, so that the cost of clock synchronization is reduced. Wherein the clock synchronization is realized by only depending on FPGA soft logic in a pure digital mode, and does not depend on an additional analog circuit.

The invention provides an automatic testing method and device for an electric energy meter, and belongs to the technical field of electric energy meter testing. The automatic test method for the electric energy meter comprises the following steps: S1, constructing a test case library corresponding to test requirements of at least one type of electric energy meter; s2, an analog circuit capable of simulating a plurality of operation behaviors of the electric energy meter is arranged on the analog signal board; s3, a corresponding test case is matched in the test case library according to the test requirement of the to-be-tested electric energy meter; and S4, controlling the analog signal board to output a corresponding analog operation signal according to the test case, and obtaining a test result corresponding to the to-be-tested electric energy meter according to the analog operation signal. According to the method, manual operation is replaced by an implementation mode of converting test process operation, different test operations are converted into signals to be input into the sampling points of the electric meter, so that the purpose of realizing related tests is achieved, the test cost is reduced, the test precision and reliability are improved, the test efficiency is improved, and compared with manual test, the method can stably run for a long time.

The neuron Logic Gate Metal-Oxide-Semiconductor (νLGMOS) circuits to mimic neurons' “integrate-and-fire” behaviors in biological neural network system can be fabricated with industry Complementary Metal-Oxide Semiconductor (CMOS) logic process technology, with which digital computational circuits are fabricated. A processing system having analog νLGMOS circuits, conversion circuitry and digital circuits optimized for power and cost for varieties of applications can be then fabricated with the same CMOS logic process technology for IC chips. Meanwhile analog νLGMOS circuits inspired from biological neural network systems can be simulated, designed, and fabricated for IC chips for the applications of biomedical fields.