The invention belongs to the field of design of an integrated circuit and relates to a nonlinear circuit time domain model reduction method and a nonlinear circuit time domain model reduction device. The method comprises the following steps of: forming a track in a state space through a 'training signal', and selecting an expansion point on the track to approach a nonlinear circuit through a segmented linear method; and obtaining a final reduction model through a time domain model reduction method based on wavelet collocation. The device comprises an input unit, an output unit, a program storage unit, an external bus, a memory, a storage management unit, an input/output bridging unit, a system bus and a processor. A nonlinear system is directly subjected to model reduction in a time domain, the time domain reduction accuracy of the nonlinear system can be guaranteed, and a time domain error can be controlled; therefore, an accurate and compact reduction model can be acquired, and the simulation accuracy and efficiency are improved.