The invention relates to the technical field of analog-to-digital
converters, and particularly discloses a
capacitance mismatch background digital
correction method applied to a high-precision successive comparison analog-to-
digital converter (SAR ADC). In order to solve the problems of limited calibration range and low convergence speed in the traditional correction technology, the invention provides a correction scheme combining a split ADC structure and disturbance reverse injection. The method comprises the following steps: constructing a complementary segmented
capacitor array, inserting redundant capacitors, and optimizing
weight distribution through
capacitor sorting grouping and bridging; a dual-channel Split ADC is used for synchronous sampling, a disturbance
signal is generated and reversely injected, and the
capacitance weight is dynamically adjusted in combination with a least
mean square (LMS) iterative
algorithm; iteration is carried out until the output difference value of the two channels is zero, the real
capacitance weight is obtained, and a correction result is output. The non-linear mismatch calibration range is expanded through the disturbance
signal, the convergence speed is remarkably improved, and the normal conversion process of the ADC does not need to be interrupted.
Simulation shows that after correction, the
effective number of bits (ENOB) is increased to 15.75 bits from 9.09 bits, the
signal-to-
noise distortion ratio (SNDR) reaches 96.60 dB, convergence is completed in a 15k sampling point through the
algorithm, and the
algorithm is superior to a traditional Split ADC technology.