Neural network space mapping modeling method for packaged transistors

Abstract

The invention provides a neural network space mapping modeling method for packaged transistors. Building of accurate packaged transistor models is of vital importance on improving the precision of wireless communication system circuits. The neural network space mapping modeling method aims to overcome the shortcomings of requirements on internal structure information and high computational complexity of existing modeling methods for packaged transistors. The neural network space mapping modeling method for the packaged transistors includes dividing each packaged transistor model into an input packaged circuit module, a nonlinear circuit module and an output packaged circuit module; respectively constructing structures of the input packaged circuit modules, the nonlinear circuit modules and the output packaged circuit modules. The neural network space mapping modeling method has the advantages that characteristics of the packaged transistors can be accurately reflected by trained models, the neural network space mapping modeling method is high in simulation speed, the design cycle can be greatly shortened, and large-scale circuits can be possibly further designed.

Description

technical field [0001] The invention relates to a microwave circuit and device modeling method, in particular to the application of neural network space mapping technology in the field of microwave modeling. Background technique [0002] In order to meet the development requirements of low cost, low power consumption, high precision, high reliability, and intelligent electronic products, the structure of power transistors used in wireless communication systems is becoming more and more complex. In addition to adding multiple dies to provide power, transistors Bonding wires and MOS capacitors in internal package circuits are also increased to ensure transistor stability and performance. The coupling between the components inside the transistor and the parasitic effects of the packaging circuit should have an increasing impact on the performance of the transistor, which poses a huge challenge to the CAD modeling technology. [0003] At present, there are two main modeling met...

AI Technical Summary

Problems solved by technology

However, the existing neural network space mapping modeling method is mainly aimed at the modeling of the transistor die, and the model cannot reflect the impact of the packaging circuit on the performance of the transistor.

Images