27 results about "Transistor model" patented technology

The invention relates to the field of gallium nitride high electron mobility transistor (GaN HEMT) compact modeling, and provides a p-GaN gate HEMT model establishment method based on a physical guided neural network (PGNN) in order to solve the problem of p-GaN gate HEMT compact model development, and the method comprises the following steps: constructing a p-GaN gate HEMT transistor model by using a TCAD simulation tool, generating a model sample, and extracting simulation data; constructing a DerivNet model and a loss function based on a physical guidance neural network; and finally, performing model training by using the simulation data to obtain the p-GaN gate HEMT model based on the physical guidance neural network.

The invention discloses an automatic simulation method for a single event effect of a bipolar band-gap reference circuit, which comprises the following steps of: S1, analyzing a circuit netlist file, and extracting transistor names and node information; s2, performing direct-current characteristic simulation on the circuit to obtain a direct-current working point of each transistor, and determining the type of each transistor; s3, establishing a transistor model, and performing transistor-level single event effect simulation to obtain a transistor-level single event effect simulation result; s4, establishing a transient pulse waveform database and a peak value database; s5, screening to obtain a sensitive transistor; s6, selecting one sensitive transistor, and extracting transient pulse data corresponding to the sensitive transistor; s7, modifying the circuit netlist file, and performing circuit-level single-particle transient characteristic simulation to obtain transient characteristic simulation result data; and S8, repeating the steps S6 to S7 to obtain transient characteristic simulation result data corresponding to all the sensitive transistors. According to the invention, the weak link of the simulation device effect is positioned.

The invention discloses a reverse modeling method for an S parameter of a microwave power transistor based on a bidirectional long short-term memory neural network-long short-term memory neural network (BiLSTM-LSTM) technology, and the method comprises the five steps of data preparation, model design, hyper-parameter setting, model training and optimization, and model evaluation. According to the BiLSTM-LSTM modeling method, the core is that forward and backward and context features of data are extracted through a BiLSTM layer, time sequence dependence modeling is carried out in combination with an LSTM layer, and therefore the nonlinear mapping relation between performance parameters and S parameters of a microwave power transistor is fully excavated. According to the method, the spatial-temporal characteristics and relevance of data can be effectively captured, the precision and generalization ability of a transistor model are remarkably improved, and an efficient and accurate modeling method is provided for realizing high-performance and high-reliability circuit design.

The invention relates to the field of design and simulation of semiconductor equipment, and discloses a two-dimensional field effect transistor model based on a single-layer transition metal chalcogenide and a construction method, and the construction method comprises the steps: setting the source end and the drain end of a two-dimensional field effect transistor to be in ohmic contact with a two-dimensional material, and constructing a charge model of the two-dimensional field effect transistor; according to the relationship between the charge and the capacitance, constructing a capacitance model comprising quantum capacitance and parasitic capacitance in the two-dimensional field effect transistor based on the charge determined by the charge model; determining stray capacitance between layers of the two-dimensional transistor, converting a circuit formed by the stray capacitance into a static capacitance network, and constructing a channel voltage model of the two-dimensional field effect transistor according to the relation between capacitance and voltage; and determining a general channel current model, and combining the relationship between the voltage, the capacitance and the charge determined by the channel voltage model with the general channel current model to obtain a final channel current model. The performance and the efficiency of the low-power-consumption electronic device can be improved.

This invention discloses a quality inspection method for compact transistor models based on machine learning, belonging to the field of semiconductor device modeling and EDA. The method includes: receiving a Verilog-A model file and a JSON configuration file defining geometric dimensions and simulation parameters; performing syntax checks and generating OSDI shared objects using the OpenVAF compiler; performing physical consistency verification, including the Gummel symmetry test (GST) and energy conservation checks; extracting device-level DC and AC characteristic indicators; and conducting circuit-level benchmark tests, determining model stability through simulation time and convergence of different unit circuits. This invention constructs a full-link automated evaluation framework from syntax to physical characteristics, effectively solving the problems of physical rationality and simulation convergence of machine learning models in integrated circuit design, and significantly improving model development efficiency and reliability.

The application relates to a high-power transistor modeling method, device and computer equipment, wherein the method comprises the following steps: obtaining device test data of a plurality of small-power transistors, each small-power transistor corresponding to different sizes, and the device test data comprising test data corresponding to at least one transistor characteristic parameter; determining a data scaling strategy corresponding to each transistor characteristic parameter according to the device test data and the size of each small-power transistor; for each transistor characteristic parameter, processing the test data corresponding to the transistor characteristic parameter of a reference small-power transistor, the size of the reference small-power transistor and the size of a target high-power transistor according to the data scaling strategy corresponding to the transistor characteristic parameter, to obtain predicted data corresponding to the transistor characteristic parameter of the target high-power transistor, and accurately establishing a target high-power transistor model based on the predicted data corresponding to at least one transistor characteristic parameter of the target high-power transistor.

The invention provides a design method and system for a profound hypothermia transistor model and a medium, and the method comprises the steps: S1, determining the size of a transistor through device design; s2, layout realization: based on the sizes of the transistors, drawing MOS, CV, LOD, WPE and MIS test structures corresponding to the transistors; s3, testing and parameter extraction: based on the test structure, the transistor is tested at a deep hypothermia, various test data are obtained, and the deep hypothermia is below 10K; and S4, model establishment: designing a deep hypothermia transistor model based on a BSIM4 model and various test data, and visualizing the modeling process by using a matched HSPICE simulator. The invention provides a large-scale chip scanning test method. Modeling is carried out more accurately by obtaining statistical characteristics of chips. Meanwhile, the testing method covers CV testing, IV testing, mismatch testing, LOD testing, WPE testing and noise testing, and the reliability and integrity of modeling data are guaranteed.

The invention discloses a low-temperature transistor modeling gold sample screening method. Firstly, a transistor test structure is designed; secondly, simulating the series of transistors with specific gate lengths and gate widths to obtain a simulation result of a business model under a type corner, and counting a median value used for determining a parameter of a gold sample; and testing the plurality of transistor test structures die at room temperature, comparing the simulation result of each parameter with the actual measurement result, and obtaining an alternative sample of the gold sample according to the standard that each parameter meets the screening criterion. The method is suitable for the gold sample selection process before the low-temperature integrated circuit establishes the intensive model, the gold sample screening efficiency can be greatly improved, and a large amount of manpower and material resources and time cost are saved.

The present invention discloses an automated simulation method for single-particle effects in a bipolar bandgap reference circuit, comprising: S1, analyzing a circuit netlist file to extract transistor names and node information; S2, performing DC characteristic simulation on the circuit to obtain the DC operating point of each transistor and determine the type of each transistor; S3, establishing a transistor model, performing transistor-level single-particle effect simulation, and obtaining transistor-level single-particle effect simulation results; S4, establishing a transient pulse waveform database and a peak value database; S5, screening to obtain sensitive transistors; S6, selecting a sensitive transistor and extracting its corresponding transient pulse data; S7, modifying the circuit netlist file and performing circuit-level single-particle transient characteristic simulation to obtain transient characteristic simulation result data; S8, repeating steps S6 and S7 to obtain transient characteristic simulation result data corresponding to all sensitive transistors. The present invention achieves the location of weak links in the effects of analog devices.

The invention relates to the technical field of compact modeling of gallium nitride HEMT (high electron mobility transistor), and discloses a modeling method of a GaN HEMT compact model based on machine learning, and the method comprises the following steps: 1, constructing a GaN HEMT transistor model by using a simulation tool, and generating a model sample, each model sample comprises the following device parameters: the thickness of the AlGaN barrier layer, the Al component of the AlGaN barrier layer, the gate-source distance, the gate-source distance and the gate length; iV characteristic simulation is carried out on each model sample, and simulation data are extracted; 2, performing data preprocessing on the device parameters of each model sample in the step 1; step 3, constructing an EEHEMT model; 4, constructing a physical guidance mixed loss function; and step 5, carrying out EEHEMT model training. According to the method, automatic prediction and self-adaptive fitting of segmented parameters can be realized, so that simulation optimization and modeling of the device can be quickly and accurately realized.

The application discloses a broadband microwave solid-state power amplifier design method based on a reconfigurable matching network, and belongs to the technical field of microwave power amplifier design. The method acquires transistor model parameters and a target working frequency band, constructs an initial topology of a reconfigurable matching network containing tunable element nodes and switch switching paths, performs discretization sampling on the target frequency band to obtain a plurality of key frequency points, dynamically adjusts element values and switch on-off states for each key frequency point through an iterative search algorithm to generate a corresponding power matching parameter set, compares the power matching parameter sets of adjacent key frequency points in terms of difference degree, identifies parameter jump intervals with a difference degree exceeding a tolerance threshold, positions mismatch element nodes according to the parameter jump intervals, performs a switch path reconstruction operation, and generates a broadband matching parameter sequence. The application can effectively solve the performance deterioration problem of a broadband power amplifier matching network caused by parameter mutation when working across frequency bands.

This invention relates to the field of ferroelectric memory technology, and provides a modeling method and system for polycrystalline ferroelectric field-effect transistors (FeFETs). The method includes: structural modeling of a polycrystalline ferroelectric thin film, discretizing the polycrystalline ferroelectric thin film into multiple grains with independent crystal orientations, establishing the coordinate transformation relationship between the local crystallographic coordinate system and the global coordinate system of each grain, and using the coordinate transformation relationship to determine the influence of each grain orientation on the polarization response; based on the influence relationship, constructing a set of nonlinear partial differential equations that couple polarization and electric field based on phase-field theory; mapping the set of nonlinear partial differential equations to a ferroelectric capacitor equivalent circuit model; and combining the ferroelectric capacitor equivalent circuit model with a compact transistor model in series, achieving electrical coupling through charge continuity conditions to construct a polycrystalline ferroelectric field-effect transistor model. This method can achieve accurate modeling and thus predict the actual electrical behavior of FeFETs.

The present invention relates to an anode short-circuited lateral insulated gate bipolar transistor model, comprising: an NMOS tube M1, the source of the NMOS tube M1 is connected to the emitter of the SA-LIGBT, and the gate of the NMOS tube M1 is connected to the gate of the SA-LIGBT; an NPN transistor QN1, the emitter of the NPN transistor QN1 is connected to the drain of the NMOS tube M1, and the collector of the NPN transistor QN1 is connected to the collector of the SA-LIGBT; a PNP transistor QP1, the PNP transistor The emitter of the transistor QP1 is connected to the collector of the SA-LIGBT and the base of the NPN transistor QN1, the collector of the PNP transistor QP1 is connected to the emitter of the SA-LIGBT, and the base of the PNP transistor QP1 is connected to the emitter of the NPN transistor QN1; a controlled current source G2 has one end connected to the emitter of the NPN transistor QN1 and the other end connected to the source of the NMOS transistor M1, and the current generated by the controlled current source G2 is controlled by the current of the NMOS transistor M1. The present invention can well fit the static characteristics and switching characteristics of the device.

The invention provides a method for improving drain current temperature trend prediction precision. The method comprises the following steps: acquiring an initial model of an MOS transistor; modifying a calculation mode of at least one parameter selected from a first parameter set in the initial model to introduce a temperature dependency relationship, the first parameter set comprising a channel length dependency coefficient (a0) of the body charge effect, a gate voltage dependency coefficient (ags) of the body charge effect, and at least one grading parameter of a0 and ags; and based on the modified parameter calculation mode, obtaining an improved MOS transistor model which can more accurately reflect the trend that Id of the MOS transistor changes along with the temperature under the condition that the working voltage is smaller than the standard working voltage. According to the method provided by the invention, a new and flexible temperature dependency relationship expression is introduced into the key parameters influencing the Id-Vg curve spacing in the MOS model, so that the problem that a standard model cannot accurately predict the Id temperature trend under low working voltage is effectively solved.

This invention discloses a GRU-based small-signal modeling method for GaN HEMTs. The method includes fitting and predicting behavioral characteristics under different bias states, operating frequency conditions, and temperatures. This transistor behavioral characteristic modeling method utilizes gated recurrent unit technology. Based on the input and output variation patterns of transistors, through optimization of model parameters and data processing, it further improves the accuracy of the output behavioral characteristics of the base GaN transistor, establishing a highly accurate transistor model that effectively characterizes small-signal behavior.

The invention provides a three-dimensional chip structure integrated with a TSV (Through Silicon Via) and an inverter, a layout method and a chip, and the layout method comprises the steps: providing a silicon substrate with the TSV, and obtaining the stress distribution of the silicon substrate under a thermal load parameter; establishing a nanoring gate-all-around transistor model, sequentially arranging a plurality of N-type and P-type nanoring gate-all-around transistors on the silicon substrate around the silicon through hole, and respectively obtaining each electrical characteristic; according to a preset electrical characteristic range and electrical characteristics, obtaining a first region conforming to the N-type nanoring ring gate transistor and a second region conforming to the P-type nanoring ring gate transistor; establishing an inverter model, arranging a plurality of inverters on the silicon substrate around the silicon through hole, and obtaining direct current characteristics of the inverters; obtaining a third area according to a preset DC characteristic range and DC characteristics; and obtaining an intersection of the first region, the second region and the third region as a region in which an inverter is arranged on the silicon substrate. The performance of the three-dimensional integrated circuit can be improved.

The present invention discloses a method for implementing a Verilog-A model of field effect transistor noise considering noise correlation, and relates to the field of transistor noise technology. The method comprises: establishing a noise module of the intrinsic part of the transistor, wherein the noise module of the intrinsic part of the transistor is characterized by drain channel noise, gate induced noise, and the correlation between the two noises, converting the two related drain channel noise sources and gate induced noise sources into three unrelated noise sources, including a drain noise source, a gate noise source, and a gate correction noise source, and calculating the equivalent current of the gate-drain noise source, introducing frequency parameters and imaginary components, and embedding the noise module in the transistor Verilog-A model. The present invention breaks through the problem that the traditional modeling method based on Verilog-A is difficult to characterize the imaginary components of noise-related factors and their frequency correlation, and realizes the accurate characterization of noise correlation in the Verilog-A language.

This invention relates to a method for building transistor models based on artificial neural networks. The method involves: acquiring the transistor process type; building an initial transistor model based on the process type, the initial model including multiple ports; applying DC voltage input signals to each port of the initial transistor model and extracting the DC current output signals from each port; and fitting the DC voltage input signals and DC current output signals to a preset artificial neural network to obtain a DC transistor model. This invention uses artificial neural networks to capture the relationship between the input and output (current and voltage) of the transistor model. The model simultaneously considers both DC and AC signals. It enables high-precision modeling of transistors and significantly improves simulation accuracy while maintaining a fast simulation speed.

The invention relates to the field of gallium nitride high electron mobility transistor (GaN HEMT) compact modeling, and provides a GaN CAVET modeling method based on a physical guidance neural network in order to solve the problem of GaN CAVET device compact model development, and the method comprises the following steps: constructing a GaN CAVET transistor model by using a TCAD simulation tool, generating a model sample, and extracting simulation data; constructing a model and a loss function based on a physical guidance neural network; and finally, performing model training by using simulation data to obtain the GaN CAVET model based on the physical guidance neural network.

The present disclosure relates to a temperature-to-digital converter that fulfills the requirement of sensing temperature in applications, such as automotive, where operation in a wide temperature range is essential. Due to the dependency of the transistor models on the temperature, the conventional temperature sensors have a limited range in which they have an acceptable function. The disclosed sensor overcomes this problem by introducing a design independent of the transistor model and relies on cancelling and matching temperature non-linearity of different blocks. The approach according to the present disclosure enables the design of a temperature sensor that is operational in the never before achieved range of −55° C. to 200° C.

The invention discloses a method and system for establishing a complementary metal oxide semiconductor tube model at extremely low temperature, and the method comprises the steps: obtaining an electrical characteristic curve of a CMOS tube at least at two extremely low temperature points, or carrying out the curve fitting of a known CMOS tube of a model; on the basis of the obtained CMOS tube electrical characteristic curves of the at least two low-temperature points, predicting the CMOS tube electrical characteristic curve under the target temperature Ttarget; modeling software is adopted to carry out curve fitting parameter extraction on the CMOS tube under the Ttarget, important parameters are corrected, and an electrical characteristic curve of the CMOS tube under the Ttarget is reconstructed based on the extracted parameters and the corrected parameters; complete modeling of low-temperature electrical behaviors of the CMOS tube is further completed after parameter extraction and modeling of the CMOS tube under the Ttarget are completed through modeling software, and accurate matching of a device characteristic curve and a real physical state under the extremely low temperature is achieved.

The application discloses a method and device for evaluating the anti-magnetic interference capability of a vertical NPN transistor, a medium and equipment. The method comprises the following steps: obtaining vertical NPN transistor models with different amplification factors, applying a static magnetic field with a preset intensity range and a step length to each vertical NPN transistor model, and obtaining a collector current drop degree expression of each vertical NPN transistor model under different magnetic field environments; obtaining an output characteristic curve of the collector current of each vertical NPN transistor model under different magnetic field environments based on the collector current drop degree expression; fitting a function relationship between the collector current and the static magnetic field based on the output characteristic curve, and calculating corresponding fitting parameters; and evaluating the anti-magnetic interference capability of each vertical NPN transistor model by using the fitted function expression, accurately evaluating the influence of an external static magnetic field on the performance of the vertical NPN transistor, and providing reliable technical support for anti-magnetic interference design.

The invention belongs to the field of information communication, and particularly relates to a transistor model and a modeling method.The transistor model comprises a voltage-controlled switch and a nonlinear output resistor used for representing a GaN HEMT, an equivalent model is established for the transistor model in the two working states, the action of the voltage-controlled switch is controlled by an input driving level, and the nonlinear output resistor is used for representing the GaN HEMT. Component parameters of the transistor model are extracted according to direct current measurement and S parameter measurement under specific bias, the transistor model in the switching mode is equivalent to a circuit containing a voltage-controlled switch, and model simplification is achieved; a measurement system used for extracting the complete parameter set of the model is simple, the measurement speed is high, a large amount of data directly related to the transistor model design or process can be obtained, and the method can be applied to the design of an efficient radio frequency power amplifier.

The invention discloses a field effect transistor noise Verilog-A model implementation method considering noise correlation, and relates to the technical field of transistor noise. Comprising the steps that a noise module of an intrinsic part of a transistor is established, the noise module of the intrinsic part of the transistor is characterized by drain channel noise, gate induction noise and the correlation of the two kinds of noise, and a drain channel noise source and a gate induction noise source which are related are converted into three irrelevant noise sources; a drain noise source, a gate noise source and a gate correction noise source are included, and calculation of the magnitude of equivalent current of the gate-drain noise source, introduction of frequency parameters and imaginary components and embedding of a noise module in a Verilog-A model of the transistor are carried out. According to the method, the problem that a traditional Verilog-A-based modeling method is difficult to represent imaginary number components of noise correlation factors and frequency correlation of the imaginary number components is solved, and accurate representation of noise correlation in the Verilog-A language is achieved.

The invention discloses a method and a device for evaluating the anti-magnetic interference capability of a VNPN transistor, a medium and equipment, and the method comprises the steps: obtaining vertical NPN type transistor models with different amplification factors, and applying a static magnetic field with a preset intensity range and step length to each vertical NPN type transistor model; obtaining a collector current decline degree expression of each vertical NPN type transistor model in different magnetic field environments; acquiring an output characteristic curve of the collector current of each vertical NPN type transistor model along with the change of the magnetic field in different magnetic field environments based on the collector current drop degree expression; fitting a function relationship between the collector current and the static magnetic field based on the output characteristic curve, and calculating a corresponding fitting parameter; the function expression obtained through fitting is used for evaluating the anti-magnetic interference capacity of each vertical NPN type transistor model, the influence of an external static magnetic field on the performance of the VNPN transistor is accurately evaluated, and reliable technical support is provided for anti-magnetic interference design.

The invention particularly relates to a FeFET model co-simulation method, device and equipment and a storage medium. The method comprises the following steps: acquiring a grid voltage at a current moment; the grid voltage at the current moment is input into a preset FeFET simulation model to obtain ferroelectric layer partial voltage, and the preset FeFET simulation model is constructed by a switch nucleation limited model, an interface charge dynamic capture model and an MOSFET model; based on the ferroelectric layer partial voltage and a preset coupling solving strategy, carrying out coupling solving on the switch nucleation limited model, the interface charge dynamic capture model and the MOSFET model to obtain ferroelectric layer charges, transistor channel charges and interface capture charges; and under the condition that the ferroelectric layer charge, the transistor channel charge and the interface trapped charge meet a preset difference condition, outputting a preset update state of the FeFET simulation model at the current moment. Therefore, the problem that the simulation precision of a ferroelectric field effect transistor model is insufficient in the prior art is solved.

The technical problem to be solved by the invention is to provide the modeling method for the FDSOI-SRAM device at the extremely low temperature, and the physical behavior and the electrical performance of the FDSOI-SRAM device at the low temperature are accurately represented. In order to solve the problem, the modeling method of the FDSOI-SRAM device at the extremely low temperature, provided by the invention, comprises the following steps of: modeling and calibrating an FDSOI transistor at normal temperature; establishing and calibrating an FDSOI transistor model at extremely low temperature; and modeling the FDSOI-SRAM device at an extremely low temperature. According to the technical scheme, a foundation is laid through normal-temperature FDSOI transistor modeling and calibration, during extremely-low-temperature modeling, a thermodynamic model is adopted to couple a carrier transport equation and lattice temperature, various low-temperature physical models such as thin silicon layer mobility are incorporated, the low-temperature behavior of the device is accurately captured, and the precision of a sub-threshold region and a linear region is ensured.