Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Transistor model capable of describing high temperature and low temperature mismatching characteristics and simulation method

A high and low temperature mismatch and transistor technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of different mismatch errors and the inability of common mismatch models to reflect mismatch characteristics, etc.

Active Publication Date: 2014-06-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF3 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0020] But when the transistors are not operating at room temperature, the mismatch error between two adjacent transistors is not the same as at room temperature
In the existing mismatch macro model, since the correction formula does not include temperature correction, if the transistor operates at high temperature, the common mismatch model cannot reflect the real mismatch characteristics

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Transistor model capable of describing high temperature and low temperature mismatching characteristics and simulation method
  • Transistor model capable of describing high temperature and low temperature mismatching characteristics and simulation method
  • Transistor model capable of describing high temperature and low temperature mismatching characteristics and simulation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] The transistor model described in the present invention that can describe the high and low temperature mismatch characteristics is to add the normal temperature mismatch correction formula to the two parameter values ​​of Vth0 and u0 in the BSIM3 model parameters, which are respectively:

[0046] ΔVth 0 = avth 0 WL * agauss ( 0,1,1 ) - - - ( 1 ) ;

[0047] Δ u 0 = 1 + au 0 WL * agauss ( 0,1,1 ) - - - ( 2 ) ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a transistor model capable of describing high temperature and low temperature mismatching characteristics and a simulation method. The changing trends, along with temperature, of the transistor mismatching characteristics are analyzed on a plurality of temperature conditions respectively, a threshold voltage parameter and a migration rate parameter are selected, extra temperature correction formulas and extra temperature correction coefficients are added respectively on the basis of original correction formulas in a mismatching macro-model, fitting is conducted on the correction coefficients by the utilization of the mismatching trends, along with high and low temperature changes, of the transistor so as to enable the mismatching model to be capable of well reflecting the electrical characteristic mismatching characteristics, and high-quality reference is provided for a circuit designer.

Description

technical field [0001] The invention relates to the design field of semiconductor digital or analog circuits, in particular to a transistor model that can describe high and low temperature mismatch characteristics. The invention also relates to a simulation method of the transistor model capable of describing high and low temperature mismatch characteristics. Background technique [0002] The device process mismatch error has attracted more and more attention in recent years. The process mismatch random error is mainly divided into two parts: 1. It is mainly caused by the slight difference between the size of the device layout and the size in the actual process. Differences in electrical characteristics between the same devices; 2. Differences in electrical characteristics mainly caused by manufacturing process errors between the same devices. In summary, the main factors that affect the differences between the same devices are: [0003] a. Small differences in gate oxide ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F17/50
Inventor 王正楠
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products