Circuit simulation based on gate spacing from adjacent mos transistors

Abstract

A circuit simulation apparatus is provided with a parameter calculating tool (32) and a circuit simulator (31). The parameter calculating tool (32) is configured to extract gate spacings between gatesof a target MOS transistor and adjacent MOS transistors integrated in an integrated circuit from layout data of the integrated circuit, and to calculate a transistor model parameter corresponding toa threshold voltage of the target MOS transistor based on the extracted gate spacings. The circuit simulator (31) is configured to perform circuit simulation of the integrated circuit by using the calculated transistor model parameter.

Description

technical field [0001] The present invention relates to a circuit simulation device and a circuit simulation method, and in particular, to a technique for performing circuit simulation in consideration of changes in transistor characteristics depending on the shape of a peripheral pattern of a target transistor. Background technique [0002] A remarkable property of a highly integrated LSI transistor is that its transistor characteristics vary depending on the pattern shape of the periphery. The peripheral pattern shape of a particular transistor affects the amount of applied stress, implant dose of impurities, and actual finished dimensions of a particular transistor. Such pattern dependence of transistor characteristics is enhanced as patterns are miniaturized, possibly causing circuit failure and lowering manufacturing yield. [0003] The problem that the pattern dependence strongly affects the transistor characteristics can be solved by adopting either of the two soluti...

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Problems solved by technology

The application discloses that the effective gate length Leff of a particular transistor depends on the gate spacing defined in the design layout due to the proximity effect, and this affects the leakage current of a particular transistor

[0007] However, according to the consideration of the inventors, there are various influences on the transistor characteristics caused by the gate pitch between adjacent transistors in addition to the variation in the effective gate length Leff, and thus in Japanese Laid-Open Patent Application No. .Technical method published in JP-A Heisei 11-284170 is insufficient to perform accurate circuit simulation

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