Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Field effect transistor model parameter correction method taking shallow trench isolation into account

A field-effect transistor, model parameter technology, used in electrical digital data processing, special data processing applications, instruments, etc.

Inactive Publication Date: 2013-03-06
TSINGHUA UNIV
View PDF4 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The present invention aims to solve the problem of STI layout proximity effect that cannot be well handled in the current integrated circuit design process, and proposes a method for modifying MOSFET model parameters considering the STI structure; this method can improve the reliability of circuit simulation and increase the number of integrated circuits. design success rate

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Field effect transistor model parameter correction method taking shallow trench isolation into account
  • Field effect transistor model parameter correction method taking shallow trench isolation into account
  • Field effect transistor model parameter correction method taking shallow trench isolation into account

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0064] A specific embodiment of the present invention is given below.

[0065] 1) Use the parasitic parameter extraction tool to extract the STI structure parameters from the input layout, and obtain W=1μm, L=100nm, SA=300nm, SB=300nm, STIW=1μm, STIL=10nm;

[0066] 2) According to the STI structural parameters W, L, SA, SB, STIW, and STIL, calculate the stress σ along the channel length direction in the MOSFET channel through formulas (1) to (3) l , get σ l =-195.4MPa; Calculate the stress σ along the channel width direction in the MOSFET channel through formula (4) ~ formula (7) t ; get σ t (x)=-79.5exp(-0.0074x)-30.3MPa;

[0067] 3) Calculate the MOSFET model parameter correction amount; specifically include:

[0068] 31) The MOSFET channel stress σ obtained in step 2) l and σ t Bring it into Y.Tan's electron mobility model, and calculate the electron mobility correction amount Δμ n =-5.9%;

[0069] 32) The MOSFET channel stress σ obtained in step 2) l and σ t Brin...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a field effect transistor model parameter correction method taking shallow trench isolation into account and belongs to the technical field of integrated circuit design. The method comprises the steps that a parasitic parameter extraction tool is adopted to extract STI (shallow trench isolation) structural parameters from an input layout; the stress in the trench of an MOSFET (metal-oxide-semiconductor field effect transistor), along the length direction and the width direction of the trench is calculated according to the STI structural parameters; and the MOSFET model parameter corrections are obtained through the stress calculation, including electron mobility correction, hole mobility correction, N-MOSFET threshold voltage correction and P-MOSFET threshold voltage correction, electron saturation speed correction and hole saturation speed correction. The field effect transistor model parameter correction method taking shallow trench isolation into account can improve the reliability of circuit simulation and increase the success rate of integrated circuit design.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and relates to integrated circuit design considering layout proximity effects, in particular to integrated circuit design considering the influence of shallow trench isolation stress on circuit characteristics. Background technique [0002] In the field of integrated circuit design and manufacturing, shallow trench isolation (shallow trench isolation, STI) technology is used to achieve isolation between field effect transistors (MOSFETs). STI technology is a substitute for local silicon oxidation isolation technology and is the mainstream isolation technology for deep submicron processes. The trench of the STI structure has a relatively steep side wall, so it has a small area, which can improve the integration level of the MOSFET. And because the CMP process is used in its manufacturing process, it has very good surface flatness. In addition, the leakage current of the STI str...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 叶佐昌李小健王燕
Owner TSINGHUA UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com