Field effect transistor model parameter correction method taking shallow trench isolation into account

Abstract

The invention relates to a field effect transistor model parameter correction method taking shallow trench isolation into account and belongs to the technical field of integrated circuit design. The method comprises the steps that a parasitic parameter extraction tool is adopted to extract STI (shallow trench isolation) structural parameters from an input layout; the stress in the trench of an MOSFET (metal-oxide-semiconductor field effect transistor), along the length direction and the width direction of the trench is calculated according to the STI structural parameters; and the MOSFET model parameter corrections are obtained through the stress calculation, including electron mobility correction, hole mobility correction, N-MOSFET threshold voltage correction and P-MOSFET threshold voltage correction, electron saturation speed correction and hole saturation speed correction. The field effect transistor model parameter correction method taking shallow trench isolation into account can improve the reliability of circuit simulation and increase the success rate of integrated circuit design.

Description

technical field

[0001] The invention belongs to the technical field of integrated circuit design, and relates to integrated circuit design considering layout proximity effects, in particular to integrated circuit design considering the influence of shallow trench isolation stress on circuit characteristics. Background technique

[0002] In the field of integrated circuit design and manufacturing, shallow trench isolation (shallow trench isolation, STI) technology is used to achieve isolation between field effect transistors (MOSFETs). STI technology is a substitute for local silicon oxidation isolation technology and is the mainstream isolation technology for deep submicron processes. The trench of the STI structure has a relatively steep side wall, so it has a small area, which can improve the integration level of the MOSFET. And because the CMP process is used in its manufacturing process, it has very good surface flatness. In addition, the leakage current of the STI str...

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