Field effect transistor model parameter correction method taking shallow trench isolation into account
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TSINGHUA UNIV
- Publication Date
- 2013-03-06
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
technical field
[0001] The invention belongs to the technical field of integrated circuit design, and relates to integrated circuit design considering layout proximity effects, in particular to integrated circuit design considering the influence of shallow trench isolation stress on circuit characteristics. Background technique
[0002] In the field of integrated circuit design and manufacturing, shallow trench isolation (shallow trench isolation, STI) technology is used to achieve isolation between field effect transistors (MOSFETs). STI technology is a substitute for local silicon oxidation isolation technology and is the mainstream isolation technology for deep submicron processes. The trench of the STI structure has a relatively steep side wall, so it has a small area, which can improve the integration level of the MOSFET. And because the CMP process is used in its manufacturing process, it has very good surface flatness. In addition, the leakage current of the STI str...