Time sequence determining method and device of integrated circuit chip

Abstract

The invention provides a time sequence determining method and device of an integrated circuit chip. The time sequence determining method includes subjecting a top module and at least two submodules of an integrated circuit chip to be designed to synthesization, overall arrangement and clock network design generation; extracting a boundary time sequence model according to the clock network of the submodules and the top module; if the boundary time sequence model meets the first time sequence conditions, designing wiring of the submodules and the top module; extracting an electric parameter model according to the wired submodules and the top module; if the electric parameter model meets the second time sequence condition, splicing the submodules and the top module and extracting a transistor model; if the transistor model meets the third time sequence condition, determining the time sequence of the integrated circuit chip. By the time sequence determining method and device, different time sequence models are extracted for different stages of integrated circuit chip design, and balance between speed and accuracy of the time sequence analysis is realized.

Description

technical field [0001] The invention relates to the technical field of power electronics, in particular to a timing determination method and device for an integrated circuit chip. Background technique [0002] The physical design of integrated circuit chips is the process of mapping functional modules described in hardware languages ​​(such as Verilog, VHDL) into layouts through design. figure 1 Flowcharts for traditional physical design methods, such as figure 1 As shown, the traditional physical design method mainly includes five stages of synthesis, layout, clock network generation, routing and signoff analysis. For the first four stages, after each stage is completed, it is necessary to check whether the design meets the corresponding items. If the design rules are not satisfied, return to the previous stage to redesign and optimize, and solve possible problems in the previous stage to reduce the pressure of the final signoff analysis stage. [0003] However, with the ...

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Problems solved by technology

[0007] The present invention provides a timing determination method and device for an integrated circuit chip to solve the problem in the prior art that the speed and accuracy of timing analysis cannot be taken into account

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