Improved structure for cmos etsoi with multiple threshold voltages and active well bias capability

Abstract

A semiconductor substrate having a first type of conductivity and a top surface, a layer of oxide disposed over the top surface and a semiconductor layer disposed over the layer of oxide. A plurality of transistor devices are disposed upon the semiconductor layer. Each transistor device includes a channel between a source and a drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. A well region is formed adjacent to the top surface. The well region has a second type of conductivity. First trench isolation regions are between adjacent transistor devices that extend through the semiconductor layer. Second trench isolation regions are between adjacent transistor devices of opposite channel conductivity.

Description

technical field [0001] Exemplary embodiments of the present invention relate generally to semiconductor devices and fabrication techniques, and more particularly to utilizing extremely thin silicon-on-insulator (ETSOI) substrates to fabricate semiconductor transistor devices, such as those used in static random access memory (SRAM) and related Semiconductor transistor devices in logic circuits. Background technique [0002] In silicon-on-insulator (SOI) technology, a thin layer of silicon is formed on an insulating layer, such as silicon oxide, which is formed on a substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply BOX. For a single BOX SOI wafer, the thin silicon layer is divided into active regions by shallow trench isolation (STI) that intersects the BOX and provides total isolation for the active device areas formed in the silicon layer. For example, by ion-implanting n-type and / or p-type dopant materials into a thin silicon l...

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Problems solved by technology

Although halo implants control short channel effects, they also lead to large random doping fluctuations, increasing junction leakage and gate-induced drain leakage (GIDL), which is fatal for low-power platforms

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