Self-adaption timing sequence calibrating method of high-speed serial communication interface

A serial communication interface and communication interface technology are applied in the field of high-speed serial communication interface adaptive timing calibration and high-speed serial communication interface timing calibration to ensure data alignment and synchronization, accurate data sampling, and reduce system clock frequency. Effect

Active Publication Date: 2013-04-10
BEIJING INST OF CONTROL ENG
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Problems solved by technology

However, since each pixel data does not have a related synchronization signal, how to confirm the start and end of each pixel da...

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  • Self-adaption timing sequence calibrating method of high-speed serial communication interface
  • Self-adaption timing sequence calibrating method of high-speed serial communication interface

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Embodiment Construction

[0029] The present invention utilizes FPGA to realize, has added a kind of calibration mode for the high-speed serial communication interface, and the flow chart is as follows figure 1 shown. In the calibration mode, the sending end sends a specific command sequence, and uses sampling, comparison, calibration, and re-sampling, such a reciprocating closed-loop calibration method, to realize the dynamic adaptive adjustment of the high-speed serial data sampling by the receiving end to achieve high-speed serial The purpose of automatic calibration of interface timing is to make accurate sampling, data alignment and data synchronization at the receiving end.

[0030] The organization structure of the receiving end of the high-speed serial bus is as follows: figure 2 shown. The content of serial data transmission is divided into clock, data, and control signals, which are transmitted by different channels. The edge alignment of data and control signals and clock signals at the ...

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Abstract

A self-adaption timing sequence calibrating method of a high-speed serial communication interface is achieved by adoption of the Field Programmable Gate Array (FPGA). The method comprises the steps of setting the high-speed serial communication interface as a calibrating mode; converting serial data received by the high-speed serial communication interface to parallel data; adjusting the sampling clock phase or sampling time delay to obtain an optimal sampling point; configuring the high-speed serial communication interface by using the optimal sampling point; converting the serial data received by the high-speed serial communication interface to the parallel data again; comparing the obtained parallel data with a preset value and adjusting the parallel data latching moment according to a comparison result to enable the parallel data received by the high-speed serial communication interface to coincide with the preset value; configuring the high-speed serial communication interface by using an obtained data latching moment result; and setting the high-speed serial communication interface as a transmission mode. The self-adaption timing sequence calibrating method of the high-speed serial communication interface is easy to achieve and power consumption is effectively reduced.

Description

technical field [0001] The invention relates to a logic circuit design, in particular to a high-speed serial communication interface adaptive timing calibration method, which is suitable for timing calibration of the high-speed serial communication interface. Background technique [0002] The rendezvous and docking task has higher requirements on the pixel and image processing efficiency of optical sensitive equipment, so a higher speed serial bus is required to download the image data to the processing unit for calculation. Due to space-borne applications, it is not yet possible to obtain dedicated aerospace-grade image transceiver chips in China, so FPGA chips with radiation resistance are generally used as image transceiver and processing units. The high-speed serial bus is divided into one common clock, one control signal, and several data transmission channels. If the FPGA adopts the conventional full-synchronous design method, according to Shannon’s sampling law, the ...

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Application Information

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IPC IPC(8): H04L7/00
CPCY02D30/50
Inventor 孙强施蕾田宇斌叶有时刘群刘波吴一帆
Owner BEIJING INST OF CONTROL ENG
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