Clock driver circuit

Abstract

The invention provides a clock driver circuit. The clock driver circuit comprises successively connected input stage, double-end-to-single-end stage and driving output stage, wherein the input stage includes differential amplifiers which are the load for each other and a common mode negative feedback loop; the differential amplifiers access differential clock signals for amplification to generatea common mode voltage; the common mode feedback loop is connected to the output ends of the differential amplifiers for stabilizing the output amplitude of the common mode voltage; the double-end-to-single-end stage converts a differential sinusoidal clock signal outputted by the double-end common mode voltage into a single-end square wave clock signal; and the driving output stage includes a multi-stage-cascaded push-pull inverter, so as to increase the driving capability of the square wave clock signal. The clock driver circuit adopts differential amplifiers which are the load for each other, and any one of the two differential amplifiers acts as the load for the other, thus expanding the amplitude range of the input stage, has the capability of inhaling and supplying a large current, and improves the slew rate, so that the clock driver circuit can receive input clock signals with large amplitude and high speed.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a clock drive circuit with low jitter and high speed, which can be applied to data converters in integrated circuits with high requirements for clock circuits. Background technique [0002] With the development of high-speed and high-precision converters, the A / D converters that can realize direct high-frequency sampling have higher and higher requirements on the performance of the clock. Among them, jitter is the most important parameter in the design of the clock drive circuit. The jitter of a clock is defined as the short-term variation of a clock signal from the ideal time position at the threshold level of its logic state change. In high-speed A / D converters, the timing error caused by clock jitter often limits the maximum transmission rate of the digital I / O interface, increases the bit error rate of the signal path, and limits the dynamic range of the analog-to...

AI Technical Summary

Problems solved by technology

[0009] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a clock drive circuit, which is used

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