36results about How to "Increased circuit complexity" patented technology

A digital passband matched filter is automatically adapted to a carrier wave ω in accordance with a frequency offset of the carrier wave, to obtain a passband digital signal having no frequency distortion due to the frequency offset. Thus, a receiver in which drawbacks such as decrease of SNR and increase of circuit complexity caused by the fixed baseband/passband matched filter is obtained. Since a cosine wave generating section operates in a carrier wave frequency restoring mode and a carrier wave frequency adaptive mode, respectively, a single cosine wave ROM table can be used regardless of the respective operating modes, thereby reducing circuit complexity. Since the digital passband matched filter acts to renew the filter coefficients adapted to the carrier wave adaptive mode only, power consumption required to operate the filter can be minimized.

The present invention is provided with a plural cell including a transistor pair. The plural cells are arranged at equal intervals so as to configure a cell group. A inter-cell distance between a transistor in one of the cell and a transistor the other cell in each of adjacent cells in the cell group is equal to a intra-cell distance between one of the transistor and the other transistor in the transistor pair.

A source signal is provided. The source signal is XORed with a scrambling random signal to generate a scrambled signal. The scrambled signal is transmitted through the digital logic circuit. The scrambled signal is XORed with the descrambling random signal logically identical to the scrambling random signal to produce a descrambled signal identical to the source signal. In one embodiment, the scrambling random signal is transmitted through the digital logic circuit and used as the descrambling random signal. In another embodiment, the scrambling random signal and descrambling random signal are generated independently using pseudo-random number generators. In yet another embodiment, the scrambling random signal is self-synchronizing and is contained within the pattern of the scrambled signal.

The DCOC block is used in ZIF BB to form HPF function to cancel dc offset with a penalty of small silicon area and low power consumption. It is a LPF plus a voltage to current conversion (VIC) resistor, and can hook up with any BB opamp used in signal path, to form a feedback loop, with or without signal gain stages in the loop. The BB opamp is used as a summing point. The summing method is input current summing. The cutoff frequency of the HPF function is thus defined by the integrator, the VIC resistor, and the feedback resistor in the summing opamp. The presence of the VIC resistor can drastically reduce the integrator capacitor and resistor values and thus save silicon area or improve receiver performance.

A distributed arbitrary waveform generator (DAWG) synthesizes the target waveform using a series of narrow pulses generated by a number of pulse generators. To achieve this, it uses an input trigger signal to control all the pulse generators, each of which generates a narrow pulse (impulses) at a specific sample time, and then all the impulses are combined to generate the output waveform. The input trigger signal is distributed to each pulse generator by a trigger distribution network. Impulses generated by pulse generators can be tuned in both pulse amplitude and width, and the spacing between them can be tuned by the trigger distribution network. Therefore the waveforms generated are completely reconfigurable.

The present disclosure relates to a countermeasure method in an integrated circuit comprising at least one first logic circuit and at least one first input register supplying the first logic circuit with a datum, the method comprising steps of introducing a random datum into each first input register of the first logic circuit and of the first logic circuit reading the random datum in each first input register, then of introducing a datum to be processed into each first input register, and of the first logic circuit processing the datum in each first input register.

Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a programmable digital input signal is determined in a calibration mode and then applied to reference circuitry in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.

The present disclosure includes a first circuit that is connected between a power feed port and an antenna port, and a second circuit that is connected between the power feed port and the ground or between the antenna port and the ground. The first circuit is a circuit in which for example a first variable capacitance element is connected in series with a first inductor, and the second circuit is a circuit in which for example a second variable capacitance element is connected in parallel with a second inductor. A switch performs switching at least between a first state in which a second end of the second circuit is connected to a first end of the first circuit and a second state in which the second end of the second circuit is connected to a second end of the first circuit.

The embodiment of the invention discloses a magnetic bias restraining method and device. The method comprises the steps of: obtaining a bus voltage U1 when a transformer is subjected to forward excitation and a bus voltage U2 when the transformer is subjected to reverse excitation in a direct current-direct current transformer; determining the magnetic bias compensation amount [Delta]d1 when the transformer is subjected to forward excitation and the magnetic bias compensation amount [Delta]d2 when the transformer is subjected to reverse excitation according to the bus voltage U1 when the transformer is subjected to forward excitation and the bus voltage U2 when the transformer is subjected to reverse excitation; superposing the magnetic bias compensation amount [Delta]d1 when the transformer is subjected to forward excitation and the direct current-direct current transformer loop output duty ratio signal amount to output the superposition value to a switch tube exciting in a forward direction, and superposing the magnetic bias compensation amount [Delta]d2 when the transformer is subjected to reverse excitation and the direct current-direct current transformer loop output duty ratio signal amount to output the superposition value to a switch tube exciting in a reverse direction. According to the embodiment, the magnetic bias restraining of the transformer can be effectively achieved.

Disclosed herein is a switching regulator with a soft start circuit for suppressing an in-rush current. The switching regulator includes a peak detector configured to receive a clock signal and detect a peak voltage of the clock signal, a comparator configured to generate a soft start signal for controlling a soft start of the switching regulator based on a result of comparing a level of the peak voltage of the clock signal to a preset reference voltage level, a counter configured to switch a state of the soft start signal at a time point when a preset soft start time arrives, and a ramp voltage generation unit configured to generate a ramp voltage by adjusting a resistance of a variable resistor based on the soft start signal.

This invention introduces the negative feedback into the gate drive. It proposes a negative feedback active gate drive (NFAGD) for silicon carbide (SiC) and gallium nitride (GaN) semiconductor devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. An auxiliary P-channel MOSFET is introduced to construct a negative feedback control mechanism. Due to the negative feedback mechanism, the proposed drive can automatically attenuate the disturbance from the complementary device of the phase-leg. The negative feedback active gate drive (NFAGD) has a simple structure and easy to be realized using a push-pull drive circuit, a drive resistor, an auxiliary MOSFET and an auxiliary capacitor, without involving any additional logical circuits. Functionally, the negative feedback active gate drive (NFAGD) can automatically suppress the induced gate-source voltage and make the gate voltage of the MOSFET stable even during high-speed switching operation without sacrificing the switching speed of the MOSFET.

A battery system includes high-voltage switches, including a multi-pole contactor. Multiple packs are connectable in a series or parallel configuration via the switches. The contactor includes first and second pairs of electrical terminals separated by a respective circuit gap, with respective contactor arms simultaneously closing or opening the gaps. At all times, internal switches formed by the gaps and arms have the same ON/OFF state corresponding to the circuit gaps both being closed or both being open. Two of the contactors may be used to connect the battery packs to a DC fast-charging station, and to connect electrode terminals of the battery packs to a bus rail, respectively. An electric powertrain includes the battery system and an electrical load, including a rotary electric machine, that is connected to a power inverter and to a mechanical load.

A continuous wave radar system comprises a substrate, a transmitter disposed on the substrate, a receiver disposed on the substrate, and an isolating device comprising a plurality of metal plates parallelly disposed on the substrate between the transmitter and the receiver for isolating leakage signal transmitted from the transmitter to the receiver. The metal plates are grounded with the transmitter and the receiver via electrical connection between the metal plates and the substrate. The metal plates are so arranged that an eddy current induced in each of the metal plates is directed away by grounding when the leakage signal passes through the metal plates.

The present invention provides an IR-UWB data transmission encoding/decoding method and module. The encoding method comprises: in each unit time period lasting T seconds, receiving an N-bit of binary data of an M-bit binary data stream and generating UWB impulse radio signal having a specific frequency fi, determining and generating an amplitude value Ax of the UWB impulse radio signal having the specific frequency fi according to the remaining M-N bits binary data, and finally transmitting the UWB impulse radio signal having the specific frequency fi and the amplitude value. The decoding method corresponds to the encoding method. According to the present invention, the data transmission rate can be increased by four times compared with the conventional data transmission rate without increasing the circuit complexity, which is useful and attractive to the IR-UWB system.

An apparatus and method for adjusting a desired expression section according to input bit values in a mobile communication system that expresses only a defined partial section of the input bit values in order to make the number of output bits be less than the number of the input bits, and maps bit values included in unexpressed sections to a specific value is provided. In the apparatus and method, a measurer divides possible output bit values into at least three sections, and measures output frequencies of output bits for the respective sections for a predetermined time. A controller adjusts the desired expression section, when an output frequency for a specific section is greater than output frequencies for other sections.