56 results about "Soft-decision decoder" patented technology

A method and apparatus for decoding a linear block encoded string of information bits comprising: converting the string into a plurality of codewords. Performing hard and soft decisions on each codeword to generate a hard and soft decision vector. Computing the syndrome and finding the location of the two minimum values by Galois Field Arithmetic. Designating these values LOW1 and LOW2 and xoring with a Nc1, thus generating Nc2. Swapping Nc1 with Nc2 and determining the lowest soft decision value, Min1 and a next lowest value, Min2. The two bit locations creating Min1 are designated as MinA and MinB. MinA being replaced with Min2 minus the value MinA. MinB being replaced with Min2 minus the value at MinB. Generating an output codeword by subtracting Min1 from all other bit locations values and 2's complementing all soft values with 0 in their location. Creating the new soft value vector. Some embodiments include a system and method that organizes an encoded codeword. The encoded codeword has several codeword bits. The method receives the encoded codeword, assigns multiple codeword bits to at least one memory address in a plurality of memory addresses, and iteratively decodes the received codeword by utilizing the plurality of memory addresses in a predetermined order. The predetermined order is based on a dimension of the received codeword.

A cryptographic system for reproducibly establishing a reliable data string, such as a cryptographic key, from a noisy physically unclonable function (PUF, 110) is provided. The system comprises a hard decision decoder (150) to decode a first multiple of error correctable data words to obtain a second multiple of corrected and decoded data words and a reliability information extractor (180) to determine reliability information, e.g. soft decision information, that is indicative of a reliability of corrected and decoded data words. The system further comprises a soft decision decoder (160) configured to use the reliability information to decode at least one further correctable data word. Error correcting a PUF using reliability information decreases the false rejection rate.

An amplitude modulated optical communication system and method are disclosed that achieve bandwidth compression by making use of an n level amplitude modulation scheme in one or more frequency bands. A soft decision decoder is disclosed that provides at least two soft slicing levels between each signal level in the multiple level transmission scheme to define an “uncertainty” region therebetween. The soft slicing levels are used to evaluate the reliability of a given bit assignment. In addition to assigning a digital value based on the received signal level, one or more soft bits are assigned indicating a “reliability” measure of the output code.

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge

A wireless communication apparatus for receiving spatially multiplexed signals in which a plurality of streams are spatially multiplexed, using a plurality of antennas, includes the following elements: a channel matrix estimator for estimating a channel matrix for multiplexed channels; a spatial decoder for spatially decoding received signals each of which has been received by a corresponding antenna so as to separate the received signals into individual stream signals by obtaining an antenna weight matrix from the estimated channel matrix, and then multiplying each received signal by the antenna weight matrix; a likelihood information estimator for estimating likelihood information using the estimated channel matrix, the antenna weight matrix, and estimated noise power; and a soft decision decoder for performing soft decision decoding on each stream signal on the basis of the estimated likelihood information.

The invention provides an efficient multi-scheme ECC technology based on a polar code. The technology is called as a pre-detection scheme and used for meeting the actual application requirements and reducing decoding delay. According to the technology, balance between the decoding speed and the performance requirements can be achieved by judging the voltage diffusion condition of a current NAND flash memory and selecting a corresponding polar code decoder (such as a hard decision decoder, a quantitative soft decision decoder and a pure soft decision decoder) for different voltage distribution states.

The invention relates to a mixed iterative decoding method for an LDPC-RS two-dimensional product code in the technical field of communication system channel decoding. According to a received LDPC-RS product code block, log-SPA soft-decision decoding is conducted on LDPC codons of each row, bit soft value information after the decoding and soft value information corresponding to the edge of a bipartite graph are stored; improved WBF decoding is conducted on LDPC rows failed in the log-SPA soft-decision decoding and estimated bit error patterns of the rows failed in decoding can be returned through an improved WBF algorithm; when the estimated error patterns can be corrected by following RS, LDPC hard-decision decoding, RS+LDPC hard-decision decoding is converted; if all errors can not be corrected after one time of iteration is finished, bit soft values corresponding to the rows which is confirmed to be right after the hard-decision decoding are corrected and iteration of the next round is conducted. According to the mixed iterative decoding method for the LDPC-RS two-dimensional product code, the problem that when LDPC-RS is decoded through an SISO decoding structure, an RS soft-decision decoder is high in complexity. Meanwhile, compared with simple LDPC+RS cascading decoding, the mixed iterative decoding method for the LDPC-RS two-dimensional product code improves codon correction performance.

Being applicable to solve the issue that in current technique, demodulation procedure is too complex, the invention discloses simplified schemes for two algorithms. Scheme 1 is that using LLR algorithm and MAX-log algorithm simplifies current demodulation procedure into piecewise functions. Scheme 2 is that using minimum distance between the received signal and hard decision boundary determines amplitude of soft bits to simplify demodulation procedure further. First, the invention decomposes signal in orthogonal into first branch component, and second branch component, and then calculates their soft bits so as to accomplish soft decision-making procedure. In scheme 1, the equipment includes communication interface (CI), decomposition module (DM), judgment module (JM), computing module (CM), and output module (OM). In scheme 2, the equipment includes CI, DM, JM, CM, and OM.

Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.

Disclosed is a soft decision decoder, and a log likelihood ratio calculator for soft decision decoding and a method thereof, for realizing a generalized log likelihood ratio algorithm in consideration of channel estimation errors for performing soft decision decoding on QAM signals, which comprises multipliers for multiplying reference signals and channel estimation signals, subtractors for subtracting a receive signal of a receiver from output signals of the multipliers, first and second square calculators for squaring the subtractors' output signals and reference signals, dividers for dividing output signals of the first and second square calculators by addition values, and a comparator for comparing output signals of the dividers.

A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.

The present invention discloses a low loss interface device between coherent detection of combined frame synchronization and soft-decision decoding, which relates to a digital signal processing apparatus of anti-fading frame synchronization and low signal-noise ratio loss fading phase ambiguity demodulation. The low loss interface device is composed of an orthogonal down converter, a coherent detector, a soft-decision decoder, a low loss phase ambiguity demodulator, a frame synchronization extractor, a power supply and other components. The low loss interface device adopts a digital signal processing technique, uses frame header information of an encoder/decoder to perform phase recognizing, combines frame synchronization extraction and realizes the low loss interface between the low loss interface between the coherent detection and soft-decision decoder. And the present invention also has features of simple circuit structure, high integration degree, stabilized and reliable performance, portability, low-cost and so on. The low loss interface device is specially suitable as an interface circuit device between the coherent detection and soft-decision decoding in the long-term fading large-capacity communicating system required for low signal-noise ratio loss.

The present invention discloses a decoding device. The decoding device includes a scaling unit for adjusting a received signal according to a scaling coefficient to generate a scaled signal; a quantizer coupled to the scaling unit for generating a quantized signal by quantizing the scaled signal; a soft decision decoder coupled to the quantizer for decoding the quantized signal to generate a decoded signal; and a scaling coefficient generating unit coupled to the scaling unit for generating the scaling coefficient according to a system information of the decoding device.

A soft decision decoding method in a multiple-input multiple-output system which respectively receives two simultaneously transmitted data streams, a first transmitting symbol and a second transmitting symbol, in a first receiving signal and a second receiving signal is provided. The soft decision decoding method includes calculating common metrics corresponding to distances between first candidate symbols, which correspond to combinations of all bits that the first transmitting symbol can have, and the first receiving signal using a channel matrix corresponding to a communication channel through which the first and second transmitting symbols are transmitted and determining intermediate nodes between the second receiving signal and the first candidate symbols and nodes between the second receiving signal and second candidate symbols corresponding to combinations of all bits that the second transmitting symbol can have; selecting first nearest candidate symbols that are at a shortest distance from the intermediate nodes on a signal constellation from among the second candidate symbols and determining a soft decision metric for each bit value of the first transmitting symbol based on the first nearest candidate symbols and the common metrics; and determining second nearest candidate symbols based on a logic value of a predetermined bit of each of the second candidate symbols and the positions of the intermediate nodes on the signal constellation and determining a soft decision metric for each bit value of the second transmitting symbol using the second nearest candidate symbols and the common metrics.

The invention provides a method for generating LLR soft decision measurement in a Turbo-STBC system, wherein the Turbo-STBC system is composed of two transmitting antennas and two receiving antennas. The method is achieved through the fact that an LLR generator module is designed to be arranged on an FPGA. In a Turbo-STBC cascade system, an LLR generator enables baseband signals of a receiving end to be decoded through an STBC decoder and then inputs the baseband signals to an LLR arithmetic unit for calculations, and generated LLR soft decision measurement is used as the input of a follow-up Turbo soft decision decoder for conducting Turbo decoding. When an internal arithmetic module is designed, a parallel arithmetic idea is completely used, and the throughput of the system is improved. A hardware reusing technology is used in the design of the STBC decoder, the arithmetic unit function is guaranteed to be achieved, and meanwhile the consumption to hardware resources of the arithmetic unit is saved. A simple algorithm is used in the design of the LLR arithmetic unit, and compared with a traditional algorithm, the complexity for achieving arithmetic unit hardware is lowered.