34results about How to "Reliability issue" patented technology

An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to selected cells of the array a write bias condition during a write operation and a read bias condition to the array during a read operation, wherein the read bias condition is different from the write bias condition.

A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad.

This invention relates to a data communication system / method for use in a downhole application wherein electrical energy is supplied over a multiple-conductor power cable to a motor assembly of a downhole tool such as an electric submersible pump. A power leg coupling interfaces a surface controller of a downhole instrument to the conductors of the tool's power cable. Uplink communication of telemetry data occurs via current modulation generated by the downhole instrument and interpreted by a surface controller. Downlink communication of downhole instrument data occurs over a different communication scheme supported by the downhole and surface controllers. Downlink communication scheme provides a supply of power to the downhole instrument. Protection of downhole electronics and continuity of communication is ensured in the event of a ground fault on the power cable. Both downlink and uplink communication frequencies are adaptive based on frequencies and voltages present on the power cable.

An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I / O device have a better ESD protection capability. Accordingly, by properly adjusting the breakdown voltage of ESD device within I / O circuit, i.e. adjusting the distance between the edge of n-well and the battlement layout pattern of heavily doped regions, it will help to reduce the chip area and improve the ESD reliability.

An OLED device according to an example embodiment includes an organic light-emitting element between a lower substrate and an upper substrate. At least a part of a side surface of the upper substrate has a reverse-tapered shape configured to reduce damage to the lower substrate caused by deformation of the upper substrate due to an external impact. Accordingly, reliability issues resulting from a short circuit or burnt lines due to the deformation of the upper substrate may be resolved, improving overall reliability and productivity of an OLED device.