High-voltage tolerant power-rail ESD clamp circuit

Abstract

A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an ESD clamp circuit and, more particularly, to a high-voltage tolerant power-rail ESD clamp circuit.

[0003] 2. Description of Related Art

[0004] ESD protection is used to protect ICs from damage due to ESD events. When applied to a mixed-voltage IO interface, because there simultaneously exists more than two power supply voltages on this interface, both thin and thick gate oxide devices are usually simultaneously used with the considerations on product reliability, operating frequency, chip area, and so on. Though ICs with mixed-voltage circuits can be manufactured with both thin and thick gate-oxide devices by using extra process steps and additional mask layers, but they will increase the product cost and lower the production yield. Moreover, a thick-gate-oxide device has inferior device characteristics than that of the thin one, so that the operating frequency of chips will be li...

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