FPGA array processing board

An array processing and processing capability technology, which is applied in electrical digital data processing, special data processing applications, digital data processing components, etc., and can solve problems such as the inability to meet the high requirements of embedded system processing capability, storage capacity and interface bandwidth at the same time.

Inactive Publication Date: 2009-11-25
BEIJING INSTITUTE OF TECHNOLOGYGY
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to overcome the problem that the existing FPGA array processing board cannot meet the high requirements of the embedded system for processing capability, storage capacity and interface bandwidth at the same time, and realize a kind of FPGA array processing board by using DSP chip and multi-chip FPGA chip design

Method used

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Embodiment Construction

[0020] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0021] In the present invention, 4 FPGA processing sub-modules and an FPGA transceiver module all adopt the XC4VSX55 ​​type FPGA chip of Xilinx Company, and each FPGA has 512 DSP48 Slices, and the single-chip FPGA peak processing capacity can reach 256GMACS; each processing sub-module includes A DDR-SDRAM chipset with a capacity of 1024MB, the chipset includes 8 pieces of MT46V128M8 of Micron Company (128MB each), the data bit width is 64bit, the working frequency of the DDR-SDRAM interface can reach 167MHz, and the storage capacity of each processing sub-module The bandwidth is 2.6GB / s, and the DDR-SDRAM storage capacity of the entire FPGA array processing board is 4GB.

[0022] Four FPGA processing sub-modules and one FPGA transceiver module are fully interconnected through source synchronous interfaces, and the data transmission bandwidth bet...

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Abstract

The invention relates to a FPGA signal processing board, belonging to the technical field of digital signal processing. The processing board comprises one power supply module, four FPGA processing sub modules, one FPGA transmit-receive module, one interconnect chip set module and one FPGA load application module, the FPGA processing sub module and the FPGA transmit-receive module are connected by full interconnect mode, the interconnect bandwidth between every two modules is as high as 1.6 B/s. The processing board can implement the external multiple high speed interfaces and load the DDR SDRAM with capacity of 4GB by PCI bus, Rapid IO bus and source synchronous interface, the storage bandwidth is as high as 10688 MB/s. the FPGA on the board has flexible configuring mode by adopting the DSP+CPLD+NAND configuring combination. The invention is suitable for the condition with harsh signal processing real time performance requirement, such as radar signal processing, image processing and communication base station and so on.

Description

technical field [0001] The invention relates to an FPGA signal processing board, which belongs to the technical field of digital signal processing. Background technique [0002] FPGA array signal processing boards are mainly used in occasions that require real-time signal processing, such as radar signal processing, image processing, and communication base stations. In addition to very high interface bandwidth, these applications also have very high requirements for data processing capabilities and the depth of cached data. However, most of the current FPGA array signal processing boards cannot meet the requirements of the above three aspects at the same time. For example, the PRO-3100 processing board launched by Spectrum has only 512MB of storage capacity on board; The traditional system synchronous bus or asynchronous bus is often used for connection, which limits the bandwidth of data transmission, such as the Chameleon II-VME-R processing board of DRS Company. Conten...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/177G06F17/00G06F7/00H04L12/40G06F15/00
Inventor 谢民刘国满冀连营高梅国方秋均
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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