Bus transmission control device and method

Abstract

The invention discloses a bus transmission control device and method. The device includes a configuration component, a selection component and a plurality of bus service quality controllers; the configuration component is used to assign a bus service to each device requesting transmission Quality controller; the selection component is used to select the current bus quality of service control mode of each bus quality of service controller from the preset bus quality of service control mode; each bus quality of service controller is used to select the current bus quality of service control mode according to the current The bus quality of service control mode performs service control on the corresponding first bus link. The invention effectively improves the bus transmission efficiency of the chip.

Description

technical field [0001] The invention relates to the field of chip technology, in particular to a bus transmission control device and method. Background technique [0002] As the scale of the chip becomes larger and larger, the demand for bandwidth resources of the chip also increases exponentially, and the interconnection of IP (Intellectual Property core, intellectual property core) inside the chip becomes more and more complicated. At present, there are mainly two ways for the interconnection of components inside the chip: one way is to use the traditional cross bar mode, in which the bus service assigns a priority to each transmission bus link. When the link transmission needs to pass through a transmission exit at the same time, the arbitration controller will adjudicate through the exit in turn according to the order of the priority of the bus link from large to small; The entrance of the bus is converted into a transmission packet, and a fixed priority is assigned to ...

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Problems solved by technology

[0003] However, the service quality of the bus in the interweaving interconnection mode is low, which is not suitable for chips with ultra-large bandwidth and ultra-low latency due to factors such as poor flexibility of QoS (Quality of Service) and low network topology capabilities. interconnection bus

The data packet-based bus interconnection method mainly fixes the influencing factors of the bus service quality in the data packet header through the on-chip network system. When data transmission and distribution are performed inside the bus, it is easy to cause data packets to be delayed and cannot be received by the multiplexer. Arbitration, which leads to transmission failure; or the data packet of a certain host inside the bus occupies bus resources for a long time, causing other hosts to fail to obtain sufficient bus resources, thereby reducing bus efficiency

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