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A method, apparatus, device, and medium for cache-coherent write-back

A coherence and cache technology, applied in the computer field, can solve the problems of affecting the bus efficiency of cache coherence system and increase the bandwidth requirements of main memory, and achieve the effect of improving bus efficiency and reducing bandwidth requirements.

Active Publication Date: 2022-04-22
SUZHOU METABRAIN INTELLIGENT TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The disadvantage of the existing technology is that each write request must write data into the main memory, which increases the main memory bandwidth requirements and affects the efficiency of the cache coherence system bus.

Method used

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  • A method, apparatus, device, and medium for cache-coherent write-back
  • A method, apparatus, device, and medium for cache-coherent write-back
  • A method, apparatus, device, and medium for cache-coherent write-back

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Embodiment Construction

[0039] In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0040] Based on the above purpose, the first aspect of the embodiments of the present invention proposes an embodiment of a cache coherent write-back method. figure 1 Shown is a schematic flow chart of the method.

[0041] like figure 1 As shown in , the method may include the following steps:

[0042] S1 In response to the memory controller receiving the read request from the first processor cache and simultaneously receiving the write request from the second processor cache, determine whether the type of the read request is an exclusive request.

[0043] When the memory controller receives a read request from a processor cache, the memory controller will process the read request. If it receives a wr...

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Abstract

The present invention provides a cache consistency write-back method, device, device, and medium. The method includes: in response to the memory controller receiving a read request issued by the first processor cache and simultaneously receiving a read request from the second processor cache. write request, determine whether the type of the read request is an exclusive request; in response to the type of the read request being an exclusive request, the memory controller sends the data to be read by the first processor to the first processor; the memory controller makes the received The write request waits and sends a write completion response to the second processor; in response to the completion of the read request processing, the memory controller processes the pending write request. By using the solution of the present invention, the cache coherence system bus efficiency can be improved, and the bandwidth requirement for writing memory can be reduced.

Description

technical field [0001] The present invention relates to the field of computers, and more specifically relates to a method, device, device and readable medium for cache consistency write-back. Background technique [0002] With the wide application of multi-core processors in mobile phones, data centers and other fields, the efficiency of cache coherent system bus has attracted more and more attention. [0003] In existing cache coherence protocols, write-back requests and read requests are regarded as the same kind of requests, and there is no priority between read requests and write requests. The main disadvantage of the prior art is that data must be written into the main memory for each write request, which increases the bandwidth requirement of the main memory and affects the cache coherence system bus efficiency. Contents of the invention [0004] In view of this, the purpose of the embodiments of the present invention is to provide a method, device, device, and read...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0815G06F12/0877
CPCG06F12/0815G06F12/0877
Inventor 刘刚
Owner SUZHOU METABRAIN INTELLIGENT TECH CO LTD
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