Cross-clock domain data signal synchronization method, system and device and medium

Abstract

The invention discloses a cross-clock domain data signal synchronization method, which comprises the following steps of: in response to triggering clock synchronization, sending a data signal in a first clock domain generated by a sending end and a single-bit enable signal to a receiving end; in response to the single-bit enable signal in a first clock domain received by the receiving end, synchronizing the single-bit enable signal in the first clock domain to obtain an enable signal in a second clock domain; and acquiring the data signal in the first clock domain by using the enable signal in the second clock domain to obtain the data signal in the second clock domain. The invention further discloses a system, computer equipment and a readable storage medium. The scheme provided by the invention can be used for realizing cross-clock domain synchronization of multi-bit wide data signals in the bus.

Description

technical field [0001] The invention relates to the field of data synchronization, in particular to a data signal synchronization method, system, device and storage medium across clock domains. Background technique [0002] The system bus is an important part of the SOC chip, which is used to connect the functional modules in the chip, complete the data transmission between the modules, and ensure that the functional modules are interconnected and run together. As the scale of the SOC chip continues to increase, the data bit width between the interfaces is also increasing, and the working clock domains of the interface modules are also different, which makes the cross-clock processing in the bus become complicated and the timing is difficult to converge. In this way, the cross-clock processing logic in the system bus The design of the code presented challenges. [0003] Aiming at the cross-clock domain processing of multi-bit wide data signals in the system bus, in the exis...

AI Technical Summary

Problems solved by technology

As the scale of the SOC chip continues to increase, the data bit width between the interfaces is also increasing, and the working clock domains of the interface modules are also different, which makes the cross-clock processing in the bus become complicated and the timing is difficult to converge. In this way, the cross-clock processing logic in the system bus The design of the code presents challenges

[0003] Aiming at the cross-clock domain processing of multi-bit

Images