Cache consistency write-back method, device and equipment and medium

Abstract

The invention provides a cache consistency write-back method, device and equipment and a medium, and the method comprises the steps: in response to a situation that a memory controller receives a read request sent by a first processor cache and simultaneously receives a write request sent by a second processor cache, judging whether the type of the read request is an exclusive request; in response to the fact that the type of the read request is an exclusive request, the memory controller sends to-be-read data of the first processor to the first processor; the memory controller waits the received write request and sends a write completion response to the second processor; and in response to the completion of the read request processing, the memory controller processes the waiting write request. By using the scheme of the invention, the bus efficiency of the cache consistency system can be improved, and the bandwidth requirement of writing into the memory can be reduced.

Description

technical field [0001] The present invention relates to the field of computers, and more specifically relates to a method, device, device and readable medium for cache consistency write-back. Background technique [0002] With the wide application of multi-core processors in mobile phones, data centers and other fields, the efficiency of cache coherent system bus has attracted more and more attention. [0003] In existing cache coherence protocols, write-back requests and read requests are regarded as the same kind of requests, and there is no priority between read requests and write requests. The main disadvantage of the prior art is that data must be written into the main memory for each write request, which increases the bandwidth requirement of the main memory and affects the cache coherence system bus efficiency. Contents of the invention [0004] In view of this, the purpose of the embodiments of the present invention is to provide a method, device, device, and read...

AI Technical Summary

Problems solved by technology

The disadvantage of the existing technology is that each write request must write data into the main memory, which increases the main memory bandwidth requirements and affects the efficiency of the cache coherence system bus.

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