System and method for segmenting and regrouping data packets on basis of CLOS (Chinese library of science) switch network

Abstract

The invention discloses a system and a method for segmenting and regrouping data packets on the basis of a CLOS (Chinese library of science) switch network, and relates to the technical field of communication. The CLOS switch network comprises a plurality of input modules IM, a plurality of central modules CM and a plurality of output modules OM. Each central module CM is connected with each input module IM and each output module OM; each input module IM comprises a combined packet scheduler, a variable-length slicing unit and a routing unit; each output module OM comprises a regrouping unit. The system and the method have the advantages that the efficiency of buses can be improved, the throughput can be obviously enhanced for short packets and packets with special lengths under the conditions of identical widths of the buses and identical work efficiency of the buses, and the performance of the system can be obviously enhanced.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a system and method for dividing and reassembling data packets based on a CLOS switching network. Background technique [0002] The cell-based CLOS switching network has the characteristics of non-blocking, expandable and large capacity, and has become the mainstream of switching chips at present. The CLOS switching network includes IM (Input Module, input module), CM (Central Module, intermediate module) and OM (Output Module, output module), which can form a 3-level CLOS structure and can be easily expanded to 5-level CLOS structure. By folding, the functions of IM and OM can be realized in one chip, while the function of CM can be realized in another chip. [0003] The Ethernet data packet (Packet) is variable in length, and the maximum packet length may reach 16,000 bytes. Switching based on data packets in the switch chip will bring a large delay and require a large ...

AI Technical Summary

Problems solved by technology

But it will also bring problems: the delay to reach the same OM through different CMs may be different

For 64 bytes, 129 bytes and other packet lengths, the bus efficiency can only reach 50%

In order to meet the throughput requirements of these data packets of a specific length, the chip has to increase the bus operating frequency, which brings a lot of complexity to the entire chip design

If the bus operating frequency cannot be satisfied, the throughput of these specific length packets will become the bottleneck of the chip

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