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Asynchronous bridge and data transmission

An asynchronous bridge and asynchronous technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of affecting bus bandwidth, low bus efficiency, and unable to really support burst transmission, etc., to achieve the effect of improving bus efficiency

Active Publication Date: 2007-06-20
HUAWEI TECH CO LTD
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Problems solved by technology

[0009] But for the AHB bus burst (Burst) transmission, the asynchronous bridge in this scheme has to go through such a process as registration-request-rebuild transmission (new clock domain)-response-end for every action (beat) in the transmission, In other words, the AHB bus burst transmission is converted to a single (single) transmission for processing, and it cannot really support burst transmission
This processing method leads to low bus efficiency, which seriously affects the bus bandwidth when transferring across clock domains. Especially when the data throughput between the dual cores is large, it will be called the bottleneck of the system.

Method used

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Embodiment Construction

[0027] The invention provides an asynchronous bridge and a communication method thereof to solve the problem that the asynchronous bridge in the prior art needs to convert the AHB bus burst transmission into a single transmission for processing, thereby causing the bus efficiency to be too low. In the present invention, a bidirectional memory is added to the asynchronous bridge. Since the bus only processes one transmission (read transmission or write transmission) at a time, the read and write operations in burst transmission will not occur at the same time, so only one bidirectional memory can meet the needs. One end of the two-way memory is connected to the asynchronous slave interface, and the other end is connected to the asynchronous master interface for storing data signals during burst transmission of the AHB bus. The asynchronous slave interface and the asynchronous master interface communicate with each other through the two-way The memory performs read and write control...

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Abstract

A asynchronous bridge consists of asynchronous slave interface for emitting transmission request signal, secondary synchronous unit for secondary-synchronizing said transmission request signal, asynchronous master interface for setting up bus transmission of the second clock domain, two-way storage with its one end being connected to asynchronous slave interface and another end being connected to asynchronous master interface for storing data signal of bus burst transmission. Its data transmitting method is also disclosed.

Description

Technical field [0001] The present invention relates to chip design technology, specifically, to an asynchronous bridge between different clock domains within the chip and a method for data transmission using the asynchronous bridge. Background technique [0002] In the current SOC (System On Chip, system on chip) chips, dual-core or multi-core design architectures are commonly used, that is, the SOC chip integrates two or more processors at the same time, such as ARM processors and DSP processing. Different processors are usually connected by the AHB (Advanced High-performance Bus) bus in the AMBA (Advanced Microcontroller Bus Architecture) specification, and the processors can be connected through AHB The bus accesses the AHB interface device of the other party. However, because different processors generally work in different clock domains, the clock frequencies on the AHB bus are different and cannot be accessed directly. Instead, the synchronous conversion between the asynch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
Inventor 刘强国刘宇季渊
Owner HUAWEI TECH CO LTD
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