DRAM (Dynamic Random Access Memory) storage control method and device

Abstract

The invention discloses DRAM storage control method and device. The method comprises the following steps of: A10. decoding read and write requests and rearranging into a plurality of BANK-based read and write request arrays according to BANK addresses; A20. respectively arbitrating the read and write requests; A30. respectively generating respective read and write request commands and activating commands and / or precharge commands; and A40. sending the read and write request commands to a command bus, and on the premise of satisfying the read and write protection time limit of a DRAM, inserting the activating commands and / or percharge commands of the read and write command requests in the other BANKs based read and write request arrays before the read and write command request in the BANK-based read and write request array. In the invention, the activating commands and the precharge commands can be completely hidden in the data transmission process, and seemingly, a DRAM data bus always transmits data, and therefore, the bus efficiency of the DRAM is greatly improved.

Description

technical field [0001] The invention relates to DRAM, in particular to a DRAM storage control method and device. Background technique [0002] The terms used in the application documents are explained as follows: [0003] BANK, memory cell array; [0004] BC, bank controller, BANK control unit; [0005] MC, master controller, MC main control unit. [0006] At present, large-capacity external memories such as SDRAM, DDR SDRAM, and DDR2 SDRAM are often used in the field of data communication. The bus bandwidth of the external memory often determines the maximum bandwidth processing capability of a data communication system in actual work. Therefore, increasing the bus bandwidth of DRAM is one of the important ways to improve the bandwidth processing capability of the data communication system. [0007] Such as figure 1 As shown, DRAM is composed of memory cell array 100 , command decoder 101 , BANK address decoder 103 , row address decoder 102 , column address decoder 104...

AI Technical Summary

Problems solved by technology

[0013] The technical problem to be solved by the present invention is to solve the problem of further improving the bus efficiency of DRAM

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