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Method for dynamically and fairly partitioning shared cache based on chip multiprocessor

A multi-core processor, dynamic technology, applied in the direction of resource allocation, multi-programming device, etc., can solve the problem of lack of fairness in the system

Inactive Publication Date: 2010-06-16
BEIJING UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0016] In order to solve the problem of lack of fairness in existing systems, the object of the invention is to provide a dynamic division method based on multi-core processor shared cache on a chip to effectively improve system fairness

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  • Method for dynamically and fairly partitioning shared cache based on chip multiprocessor
  • Method for dynamically and fairly partitioning shared cache based on chip multiprocessor
  • Method for dynamically and fairly partitioning shared cache based on chip multiprocessor

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Embodiment Construction

[0065] Taking an on-chip multi-core processor as an example, the method of the present invention will be described in detail below. The processor configuration is shown in Table 1:

[0066] Table 1 CMP configuration

[0067]

[0068] On this processor, the four parameters take the value S respectively rollback =10%, S repartition =1%, gran=64B and t=1000000, the specific division steps are as follows:

[0069] (1) Initialization:

[0070] 1.1) All threads equally divide Cache, Pi=512KB / 4=128KB;

[0071] 1.2) According to the current computer architecture, then M 1 =0.1,E 1 =3,E 2 =6,E 3 = 158 and CPI base =0.5

[0072] 1.3) Calculated = CPI base +E 1 +M 1 ×E 2 = 4.1 and β = E 3 =158;

[0073] (2) Backtracking stage:

[0074] 2.1) Calculate the fairness index S of the current division scheme 2 , currently the first time slice, S 2 1 = 1.38;

[0075] 2.2) If the current time is the end of the first time slice, then let S 2 0 =1000000;S 2 1 2 0 , go t...

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Abstract

The invention relates to a method for dynamically and fairly partitioning shared cache based on a chip multiprocessor, and belongs to the field of computer architectures. Fairness is a key optimization problem; when a system lacks of the fairness, problems such as starvation of a thread and priority inversion may take place. But the current design of CMP mainly aims to improve throughput of the system, so the fairness of the system can be sacrificed generally. The invention provides a new fairness parameter and a division method. The partitioning method comprises three steps: initializing, roll-backing and repartitioning, wherein at the initializing stage, the cache is equally partitioned before the running of the thread; at the roll-backing stage, the partition which is repartitioned forthe previous partition but has reduced fairness is canceled; and at the repartitioning stage, the cache is newly partitioned for all the threads if no roll-backing occurs and the fairness parameter is greater than a repartition threshold. The partitioning method for the shared cache provided by the invention remarkably improves the fairness of the system; and the throughput of the system is also improved slightly.

Description

technical field [0001] The invention belongs to the field of computer architecture, and in particular relates to a dynamic fair division method based on shared cache of on-chip multi-core processors. Background technique [0002] Multi-core processors have become an important trend in the development of microprocessors in the future. At present, most mainstream on-chip multi-core processors (chip Multiprocessor, referred to as CMP) mostly use private first-level (or first-level and second-level) Cache (that is, high-speed cache), shared The on-chip storage structure of the secondary (or tertiary) Cache. This structure maximizes resource utilization and avoids repeated overhead by sharing the secondary (or tertiary) Cache and lower storage layers. However, as the number of concurrent execution threads increases, the pressure on the storage layer continues to increase. Recent studies have shown that the conflicting access of the shared cache has a great impact on the perform...

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Application Information

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IPC IPC(8): G06F9/50
Inventor 方娟蒲江
Owner BEIJING UNIV OF TECH
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