Performance-imbalance-monitoring processor features

Abstract

The current application is directed to architected hardware support within computer processors for detecting and monitoring various types of potential performance imbalances with respect to simultaneously executing hardware threads in simultaneous multi-threading (“SMT”) processors and SMT-processor cores. The architected hardware support may include various types of performance-imbalance-monitoring registers that accumulate indications of performance imbalances and that can be used, by performance-monitoring software and by human analysts to detect performance-degrading conflicts between simultaneously executing hardware threads. Such conflicts can be ameliorated by changing the scheduling of virtual machines, tasks, and other computational entities, by redesigning and re-implementing all or portions of performance-limited and performance-degrading applications, by altering resource-allocation strategies, and by other means. In addition, performance imbalance detection and monitoring can be used to provide accurate, computational-throughput-based accounting in cloud-computing environments.

Description

TECHNICAL FIELD[0001]The current application is directed to hardware facilities within processors that facilitate performance monitoring and accounting and, in particular, to performance-imbalance-monitoring features that store indications of potential imbalances in performance and imbalances in resource utilization by hardware threads within multi-threaded processors and processor cores.BACKGROUND[0002]Many modern processors include a large number of architected performance-monitoring registers that are used to count the occurrences of performance-impacting events, including resource-exhaustion-related events, and to measure computational throughput. Resource-exhaustion events include many different types of performance-impacting conditions that arise during processor operation, such as cache-line eviction events, cache misses, delays in storing data or launching operations due to full queues, and delays in accessing data and launching operations due to empty queues. In many modem ...

Images