10 results about "Bus error" patented technology

The invention relates to the technical field of industrial automation electronic testing, in particular to an industrial control mainboard anti-interference performance evaluation system and method for a complex disturbance scene, and the system comprises a clock disturbance scene generation module, a dynamic clock interference injection module, a clock bus deterioration collection module and an anti-interference level output module. Wherein the clock disturbance scene generation module is used for generating a clock disturbance spectrum; the dynamic clock interference injection module is used for converting the clock disturbance spectrum into a frequency-phase dual-modulation signal and injecting the frequency-phase dual-modulation signal into the tested industrial control mainboard; the clock bus deterioration acquisition module is used for acquiring bus error code characteristics caused by clock disturbance in real time; and the anti-interference level output module is used for generating a four-level clock anti-interference level. According to the invention, by constructing a closed-loop system of disturbance injection-feature acquisition-grade evaluation, quantitative evaluation and stability determination of the anti-interference capability of the industrial control mainboard in a complex disturbance scene are realized.

The embodiment of the invention discloses a chip, a PCIe link error processing method and a chip system, relates to the technical field of integrated circuits, and aims to facilitate accurate fault isolation and reduce the service interruption range. The chip comprises: a link error processing module configured to keep a PCIe port in a connection state in response to a detected downstream link error event of the PCIe port of the chip, and send an interrupt signal to an on-chip microcontroller through an internal bus of the chip; the interrupt signal carries an error source identifier for indicating a bus number, an equipment number and a function number of the fault equipment; the on-chip microcontroller is configured to search a device tree topology table corresponding to the PCIe port according to the error source identifier, and locate a target port to which a bus connected with the fault device belongs; and disconnecting the PCIe link between the fault device and the target port through the link control register of the target port. The PCIe bus error detection method and device are suitable for the scene of PCIe bus error detection.

Bus error handling method This description relates to a bus error handling method, in which one or more first characteristics of a first write transaction (410) destined for a functional unit (116) and passing through a gateway (160,162,164,166,168) are stored, and in which, in the presence of a bus error sent by the functional unit (116): - one or more second characteristics related to said error are stored; - the gateway (160,162,164,166,168) generates a first interrupt (416,420,422,430) which it transmits with said first and second characteristics to a management unit (440); and - the management unit (440) generates at least one second interrupt (SBS_IRQ_NS, SBS_IRQ_SEC) destined for a processing unit (110, 312, 314) depending on the first and / or second characteristics. Figure for the abbreviation: Fig. 4

The invention discloses a CAN bus error frame detection positioning system and method, and relates to the technical field of CAN buses. Aiming at the problems that the traditional CAN bus error frame checking depends on data analysis, oscilloscope detection or one-by-one controller plugging and unplugging, the operation is tedious, and controllers with special installation positions are difficult to process, the method provided by the invention realizes rapid positioning of an error frame source by collecting waveform characteristics of each controller and utilizing AI analysis. According to the technical scheme, the method comprises the steps of waveform data acquisition, AI feature marking, error frame waveform interception and source identification, error frame positioning can be automatically completed, the troubleshooting efficiency is improved, the operation difficulty is reduced, and the method is suitable for fault diagnosis of various vehicle CAN bus systems.

The present application relates to the technical field of industrial automation electronic testing, and specifically relates to an industrial control mainboard anti-interference performance evaluation system and method for a complex disturbance scene, comprising a clock disturbance scene generation module, a dynamic clock interference injection module, a clock bus degradation collection module and an anti-interference level output module; wherein: the clock disturbance scene generation module is used to generate a clock disturbance spectrum; the dynamic clock interference injection module converts the clock disturbance spectrum into a frequency-phase double modulation signal and injects it into the industrial control mainboard under test; the clock bus degradation collection module is used to collect bus error code features caused by clock disturbance in real time; and the anti-interference level output module is used to generate a four-level clock anti-interference level. Through the construction of a closed-loop system of disturbance injection-feature collection-level evaluation, the present application realizes quantitative evaluation and stability determination of the anti-interference capability of the industrial control mainboard under a complex disturbance scene.

The invention discloses a bus error frame identification method and device and a readable storage medium. The method comprises the following steps: acquiring a differential voltage signal and a corresponding current signal of a CAN bus node; performing continuous dominant bit signal extraction on the differential voltage signal based on a dynamic analysis window to obtain an abnormal frame differential voltage signal and a corresponding abnormal frame current signal; determining a voltage change sequence according to the abnormal frame differential voltage signal, and determining a current direction mark according to the abnormal frame current signal; and determining node driving characteristics according to the voltage change sequence, determining a node driving state according to the current direction mark, and determining an error frame identification result according to the node driving characteristics and the node driving state. Through cross validation of the node driving characteristics determined by the voltage change sequence and the node driving state determined by the current direction mark, node-level bus error frame positioning can be realized, and the bus error diagnosis precision is improved.

The invention relates to the technical field of computers, in particular to an equipment fault processing method and device, equipment and a medium, and the method comprises the steps: obtaining error information of a target error type of a high-speed serial bus error; error reporting equipment is determined according to the error reporting log, and a fault source is accurately positioned; for each piece of error reporting equipment, a historical error reporting log set and a current error reporting log are combined, so that the fault type is accurately judged; based on the fault type, an optimal equipment parameter combination is determined through a parameter optimization model, and the model dynamically adjusts SI parameters through an algorithm; and the equipment is removed and re-accessed under the preset condition, so that certain fault repair is completed, the fault processing efficiency and accuracy are remarkably improved, and meanwhile, the performance degradation risk of the equipment caused by the fault is reduced.

The invention discloses a real vehicle bus error frame positioning method, device and equipment and a storage medium, and relates to the technical field of automotive electronics and vehicle-mounted network communication, and the method comprises the steps: obtaining a diagnosis service request and register packaging mapping; performing functional addressing based on the diagnosis service request to identify a target register error timer, accessing the register encapsulation mapping to read a target register mapping value, and determining a target error counter value set and a target receiving error counter value set; and based on the target error counter value set and the target receiving error counter value set, triggering fault analysis to position a real vehicle bus error frame, determining a bus error frame detection result, and based on the bus error frame detection result, completing real vehicle bus error frame positioning. According to the method, the target mapping value is read by using the timer for identifying the error of the target register through function addressing, fault analysis is triggered to accurately position the fault source of the error frame of the real vehicle bus, the troubleshooting efficiency is remarkably improved, the troubleshooting cost is reduced, and misjudgment is avoided.

The present invention provides a power supply controller and a direct grid-connected control method. The power supply controller includes an S3R, a BCDR, and a bus error amplifier. The S3R is connected to a first bus error amplifier, and the BCDR is connected to a second bus error amplifier. The present invention has the following beneficial effects: the BCDR and S3R each have independent bus error amplifiers, achieving decoupling of their loop designs, making the design more flexible, facilitating improved bus dynamic characteristics and stability, and enhancing power scalability. Furthermore, the power scalability of the power supply controller is further improved through a direct grid-connected control method using dual power supply controllers. This grid-connected method does not require the addition of a separate grid-connected controller, thus enabling power expansion without increasing the weight of the entire satellite. Furthermore, this method can be extended to grid-connected control with multiple power supply controllers.

The receiving circuit has a clock generator circuit, a synchronization circuit, and a controller. The clock generator circuit is configured to generate a fundamental clock signal having a fundamental frequency. The synchronization circuit is configured to synchronize an edge in the base clock signal with an edge in the Manchester encoded data signal received through the serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a sequence start condition of a first type indicating a transaction of the first type during which the first pulse has a pulse duration defined for the sequence start condition of the first type. The Manchester encoding data signal is received through a serial bus; configuring the first timer to expire after the first timeout period; and ignoring the first pulse when signaling consistent with the sequence start condition of the first type has not been received before expiration of the first timer.