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Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus timing improvements

An error-correcting code, bus transmission technology, used in communication or storage device bus to transmit data, across the computer field

Inactive Publication Date: 2007-12-05
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Finally, while the previously disclosed basic structure offers advantages over the CRC / alternate approach, creating ECC and making it fit the needs of the system is not always a significant i.e. extraordinary effort

Method used

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  • Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus timing improvements
  • Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus timing improvements
  • Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus timing improvements

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Embodiment Construction

[0021] Some of the methods and apparatus provided by some exemplary embodiments generate bus error correction code (ECC) for a bus of m transfer stages, where m is greater than 1 (i.e., a data word is transferred over two or more bus cycles, and in the bus ECC code word some or all of the different ECC codewords). Several exemplary embodiments generate nested sets of 2-bit sign codes that preserve and / or modify portions of the original SEC / DED code and provide timing improvements for the newly generated S2EC / D2ED check bits as they pass over the bus.

[0022] Several exemplary embodiments include methods of constructing nested error correction code (ECC) schemes. The method includes receiving a Hamming distance n code including an original check digit. Defining the sign-correction code H-matrix framework includes specifying bit positions for the original check bits as well as additional check bits associated with the sign-correction code. Assign bit positions such that these...

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Abstract

Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

Description

technical field [0001] The present invention relates to transferring data across a computer, communication or storage device bus, and more particularly to protecting data using nested error correcting code (ECC) schemes. Background technique [0002] In the past, it was common for computer systems to use several wide parallel buses with many bits or bit lanes in a parallel architecture. These buses deliver data words from source to receiver in one transfer. So, for example, a common bus would deliver 64 data bits to its destination per transfer cycle. Such a bus can be used on a chip, on a module, or on a single board. In the past, it was also common for communication systems to use narrow single-wire buses with only one bit lane per bus. These buses deliver their data word from a single source to a single (or multiple) recipients over many transfer cycles, sending one bit down the channel bit by bit, until the entire payload, or data word, is delivered. [0003] To ensu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/00H04L29/02
CPCH03M13/2906H03M13/098H03M13/19
Inventor 蒂莫西·J·戴尔帕特里克·J.·米尼
Owner INT BUSINESS MASCH CORP
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