Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus timing improvements

An error-correcting code, bus transmission technology, used in communication or storage device bus to transmit data, across the computer field
CN101083514AInactive Publication Date: 2007-12-05INT BUSINESS MASCH CORP

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
INT BUSINESS MASCH CORP
Publication Date
2007-12-05
Estimated Expiration
Not applicable · inactive patent

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Abstract

Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.
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Description

technical field

[0001] The present invention relates to transferring data across a computer, communication or storage device bus, and more particularly to protecting data using nested error correcting code (ECC) schemes. Background technique

[0002] In the past, it was common for computer systems to use several wide parallel buses with many bits or bit lanes in a parallel architecture. These buses deliver data words from source to receiver in one transfer. So, for example, a common bus would deliver 64 data bits to its destination per transfer cycle. Such a bus can be used on a chip, on a module, or on a single board. In the past, it was also common for communication systems to use narrow single-wire buses with only one bit lane per bus. These buses deliver their data word from a single source to a single (or multiple) recipients over many transfer cycles, sending one bit down the channel bit by bit, until the entire payload, or data word, is delivered.

[0003] To ensu...

Claims

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