Method and system for fault isolation for PCI bus errors

A PCI bus, error technology, applied in the field of fault isolation, can solve the problems of difficult fault isolation, wide performance range, large number, etc., to achieve the effect of reducing fuzzy judgment

Inactive Publication Date: 2004-04-21
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although standard facilities have the ability to catch errors, the number of possible failure conditions is large, thus making the PCI architecture allowable performance range wide
This makes it very difficult to isolate the fault to the specific faulty component

Method used

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  • Method and system for fault isolation for PCI bus errors
  • Method and system for fault isolation for PCI bus errors
  • Method and system for fault isolation for PCI bus errors

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Embodiment Construction

[0016] The present invention relates to fault isolation for PCI architectures. The following description is written to enable one of ordinary skill in the art to make and use the invention, and is written in accordance with the terms and requirements of the patent application. Those skilled in the art will readily appreciate that various modifications can be made to the preferred embodiment and that the general principles herein can be applied to other embodiments. Therefore, the present invention is not limited to the embodiments presented here, and its application scope is extremely wide according to the basic principles and performances described here.

[0017] figure 1 A basic block diagram of a general purpose computer system to which the invention may be applied is shown. As shown in the figure, the computer system of the present invention has a processor 10 (such as a Power PC processor produced by IBM Corporation) coupled to memory 12, namely RAM (Random Access Memor...

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Abstract

Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input / output (I / O) subsystem formed by a plurality of I / O devices communicating via the bus, includes categorizing, in a recursive manner, the I / O subsystem, and isolating a source of an error condition within the I / O subsystem. Further, the I / O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input / output mechanism, coupled to the processing mechanism.

Description

[0001] The present invention is related to the following invention patent applications: [0002] Application Number topic Date of Application 08 / 829,017 (JAS675R) Processing method and processing system for error detection shutdown error March 31, 1997 08 / 829,018 (JAS677P) available and unavailable software to read the computer system Fault Isolation Register Error Collection Adjustments March 31, 1997 08 / 829,016 (JAS678P) fault isolation in computer systems machine inspection processing March 31, 1997 08 / 829,089 (JAS679P) Method and system for recovering a reboot program March 31, 1997 08 / 829,090 (JAS693P) Supervise electronic computer systems Methods and systems for operations March 31, 1997 technical field [0003] This invention relates generally to input / output operations of computer systems, and more particularly ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/00G06F11/22G06F11/267G06F13/00
CPCG06F11/221G06F11/2205G06F11/2273
Inventor C·A·麦劳克林A·基特阿蒙
Owner IBM CORP
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