Differential power consumption analysis shield circuit for DES encrypted chip

Abstract

This invention relates to a differential power loss analysis screen circuit applied in the DES ciphered chips composed of a screen unit and a complementary register unit to be connected with each other combining the basic structure of the DES ciphered plan. This invention is mainly against the cryptographic key of the 16-turn operation of the DES ciphered flow, the operation results of the 15-turn are sent to registers L15 and R15, in which, L15 is composed of two parts: an ordinary one of 28 bit and complementary one of 4 bit, part results of the 15-turn operation, the sub- cryptographic key of the 16-turn and the preset false sub-cryptographic key are sent to the screen unit.

Description

technical field [0001] The invention belongs to the technical field of information security, and in particular relates to a defense circuit of an encryption chip against differential power analysis attacks. Background technique [0002] With the rapid development and popularization of smart cards and computer networks, information security issues have become increasingly prominent, so various forms of dedicated cryptographic circuits and cryptographic algorithm processors are widely used in various products. At present, commonly used cryptographic algorithms can be roughly divided into two categories: symmetric algorithms represented by DES and AES and asymmetric algorithms represented by RSA and ECC. DES (Data Encryption Standard) is currently a very widely used data encryption method. It was adopted by the National Bureau of Standards in 1977 as the No. 46 Federal Information Processing Standard. [0003] Any security product or cryptographic system must face a problem of...

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Problems solved by technology

[0014] Regarding how to resist differential power analysis, researchers have proposed a variety of solutions, such as increasing circuit noise, data shielding, and designing circuits based on logic and asynchronous logic based on sensitive amplifiers, etc., but these solutions need to introduce additional noise and random numbers. Change the algorithm flow, even change the mainstream design logic

The key to resisting differential power analysis is to reduce its signal-to-noise ratio. A direct method is to add circuit noise, but the noise generating circuit will increase the power consumption of the circuit, and it is also very difficult to determine how much noise needs to be added to defend against differential power analysis. Therefore, from another perspective, trying to reduce the value of the differential power signal can also reduce the signal-to-noise ratio of the differential power analysis. If the power difference in different states of the circuit tends to zero, the differential power analysis will fail

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