TDC (time/digital conversion) method and device based on FPGA (field programmable gate array) fine delay unit

Abstract

A TDC (time / digital conversion) method based on an FPGA (field programmable gate array) fine delay unit is characterized in that a laser pulse trigger signal FRIG_IN (1) is processed by a substrate wiring delay (2) before reaching to a buffer BUFR (3) and is processed by a 64-line wiring delay (4) before reaching a 64-level fine delay unit IODEALY module (5); 1tap (78ps) is added to each level or each line of a fine delay unit IODELAY in order; delay precision of the 64-level fine delay unit IODEALY module (5) is controlled via a delay correcting unit IDELAYCTRL module (6); a signal subjected to bilateral sampling is processed by OR logic (10) into a primary judgment signal of a trigger signal; the primary judgment signal is processed by a 4-bit shift register 4bit shift reg (12), equal 0 logic (13) and AN gate logic (14) finally into a signal TRIG_OUT (15).

Description

technical field [0001] The invention relates to the field of high-precision time measurement, in particular to a time-to-digital conversion method and device based on an FPGA fine delay unit. Background technique [0002] When high-precision time measurement is applied to a multi-channel laser three-dimensional radar system, the delay relationship between the optical path trigger pulse and the system clock in each channel is obtained, so as to obtain the precise arrival time of multi-channel data in the laser three-dimensional radar (time-to-digital conversion) , so as to pave the way for the subsequent point cloud imaging technology. [0003] In the traditional time-to-digital conversion TDC design architecture, using the carry chain as a delay tap to obtain highly accurate delay information has been widely used. However, this TDC based on the carry-chain structure is limited by the uniformity of the delay taps. Different ambient temperatures and different FPGAs will chan...

AI Technical Summary

Problems solved by technology

However, this TDC based on the carry chain structure is limited by the uniformity of the delay taps

Different ambient temperature, different FPGA will make the delay tap change, which is the main limiting factor to improve TDC performance

TDC based on ASIC technology, its functional structure is fixed, but its precision is low, cost is high, and scalability is low

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