Memory circuit

Abstract

When to a memory cell array 21 a read / write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates to a memory circuit having an error correcting function, and more particularly, to a memory circuit which is tough to a multi-bit error in which a plurality of bit errors generates locally.[0003]2. Description of the Prior Art[0004]FIG. 7 is a circuit configuration for illustrating a conventional memory circuit having an error correcting function (hereinafter, simply called memory circuit). In FIG. 7, a reference numeral 11 represents a memory cell array. A reference numeral 12 represents a memory cell. A reference numeral 13 represents a sense amplifier circuit. A reference numeral 14 represents an ECC (Error Check and Correction) circuit. In such a memory circuit, parity bits of n bits are added to data of m bits, where n represents a positive integer which is not less than one, and m represents a positive integer which is not less than two. When an error occurs in at least one bit on carrying o...

AI Technical Summary

Benefits of technology

[0048]The above-mentioned division number K′ represents a distance (worst value) between error bits which cause the memory circuit a data error, in case where the particle is plunged parallel to the word line. The multi-bit soft error hardly occurs on using the division number K′ which is calculated as described above.

[0048]The above-mentioned division number K′ represents a distance (worst value) between error bits which cause the memory circuit a data error, in case where the particle is plunged parallel to the word line. The multi-bit soft error hardly occurs on using the division number K′ which is calculated as described above.

[0048]The above-mentioned division number K′ represents a distance (worst value) between error bits which cause the memory circuit a data error, in case where the particle is plunged parallel to the word line. The multi-bit soft error hardly occurs on using the division number K′ which is calculated as described above.

[0048]The above-mentioned division number K′ represents a distance (worst value) between error bits which cause the memory circuit a data error, in case where the particle is plunged parallel to the word line. The multi-bit soft error hardly occurs on using the division number K′ which is calculated as described above.

Problems solved by technology

By the way, the above-mentioned data error (bit error) may locally occur.

Such a data error may be called a soft error.

When the electron is absorbed into a latch node of the memory cell, the datum is destroyed in the memory cell so that the soft error occurs.

In the other words, the soft error is an error in which the data are locally destroyed in only parts into which the alpha ray or the neutron ray is plunged.

In as much as electrons, which are generated in the semiconductor substrate by each particle of the alpha ray and the neutron ray, have charges of 20 f-coulombs to 200 f-coulombs, there is a growing possibility that errors simultaneously occur in adjacent memory cells by the plunge of one particle.

Inasmuch as the data of (m+n) bits are read out of the memory cells of (m+n) that are adjacent to one another, in the conventional memory circuit, there is a drawback in which makes it impossible to correct the errors when the multi-bit soft error occurs in which a plurality of bit errors generates locally and simultaneously, as described above.

In other words, there is a drawback in which makes it impossible to correct the errors when bit errors having a bit number greater than a correctable one occur simultaneously due to the multi-bit soft error.

For example, there is a drawback in which it is impossible to correct the errors when the errors simultaneously occur in two bits due to the multi-bit soft error in the adjacent data of 7 bits as described above.

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