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Time-sharing digital error correction circuit device of high-speed flow line type analog-digital converter

A technology of analog-to-digital converters and error correction circuits, applied in the direction of analog-to-digital converters, analog/digital conversion calibration/testing, etc., can solve the problems of design complexity, adverse effects of chip area, and increased circuit complexity, and achieve reduction The effect of small circuit design complexity, small amount of computation, and short delay

Active Publication Date: 2010-08-18
杭州思泰微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the number of stages increases, this method will lead to a geometric increase in circuit complexity, which will have a negative impact on design complexity and chip area.

Method used

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  • Time-sharing digital error correction circuit device of high-speed flow line type analog-digital converter
  • Time-sharing digital error correction circuit device of high-speed flow line type analog-digital converter
  • Time-sharing digital error correction circuit device of high-speed flow line type analog-digital converter

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specific Embodiment 1

[0019] Specific embodiment one: the time-sharing digital error correction circuit of the analog-to-digital converter of four-bit precision sees image 3 , which includes a three-stage multiplication digital-to-analog converter, the high and low bits of the output of the first-stage multiplication digital-to-analog converter are respectively connected to their corresponding D flip-flops, and the D flip-flops connected to the first-stage high bits are connected to the exclusive OR gate (A) input terminal, the D flip-flop (S) connected to the first-level low-level connection is connected to the input terminal of the exclusive-or gate (B), the high-level output of the second-level multiplication digital-to-analog converter is connected to the input terminal of the exclusive-or gate (B), and the first-level low-level connection After the D flip-flop (S) and the high bit of the output of the second-stage multiplication digital-to-analog converter are respectively connected to the inp...

specific Embodiment 2

[0022] Specific embodiment two: the last stage of the time-sharing digital error correction circuit of the analog-to-digital converter of six-bit precision sees Figure 4 , which includes the D flip-flop corresponding to the output of the first five bits obtained by the above four-level operation, except that the highest D flip-flop is only connected to the input terminal of the XOR gate, and the flip-flops corresponding to the other four bits are connected to other The input end of the corresponding XOR gate and the input end of the corresponding switch, the output high bit of the final multiplication digital-to-analog converter is connected to the input end of the XOR gate connected to the fifth flip-flop and the input end of the switch, and then The output terminals of the first-level switch are respectively connected to the input terminals of the previous-level switch, the input terminal of the previous-level XOR gate until the next highest level, and the switch output corr...

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Abstract

The invention provides a time-sharing digital error correction circuit device of a high-speed flow line type analog-digital converter, which meets the requirement of the extreme converting rate on transmission delay, can provide a simplified digital error correction circuit, effectively controls the chip area, reduces the complexity of the circuit design and improves the design efficiency. Analog signals are input to each level of multiplication digital-analog conversion circuit device, and the output signals of each level of multiplication digital-analog conversion circuit device comprise a high order and a low order. The invention is characterized in that by utilizing a delay link gap in time delay alignment, high orders output by the current level of multiplication digital-analog conversion circuit and all orders output by all preceding level of multiplication digital-analog conversion circuits are respectively processed by digital error correction in the respective level of digital error correction circuit, and then the high order output by the next level of multiplication digital-analog conversion circuit is processed by digital error correction by entering the next level of digital error correction circuit until complete output digital signals are finally output to finish complete digital-analog conversion.

Description

(1) Technical field [0001] The invention relates to the technical field of a pipelined analog-to-digital converter (Pipeline ADC), in particular to a time-sharing digital error correction circuit device for a high-speed pipelined analog-to-digital converter. (2) Background technology [0002] Due to its relatively moderate requirements and performance in terms of process requirements, chip area, power consumption and speed, pipelined analog-to-digital converters have achieved rapid development in recent years. Based on deep submicron complementary oxide semiconductor (CMOS) technology, the accuracy of the current pipelined analog-to-digital converter covers 8 to 14 bits, and the speed covers from 25MHz to 250MHz. Based on this structure, a single converter chip or an integrated SOC chip It is widely used in communication, industry, medical imaging and defense fields. [0003] The classic 4-stage 1.5-bit + 2-bit pipelined analog-to-digital converter system such as figure 1 ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10H03M1/14
Inventor 华玲林
Owner 杭州思泰微电子有限公司
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