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Digital error correction

An error correction and error technology, applied in the direction of data representation error detection/correction, error detection/correction, digital transmission system, etc.

Active Publication Date: 2014-06-25
OXFORD BROOKES UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these tend to be either very large, or only correct a single error

Method used

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  • Digital error correction
  • Digital error correction
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Examples

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Embodiment Construction

[0052] refer to figure 1 , in a first embodiment of the invention, the circuit 100 comprises a finite field multiplication subcircuit 105 having two parallel inputs 105a, 105b and a parallel output 105c. The multiplication subcircuit 105 is arranged to produce a product C at an output 105c. The product C is the Galois field GF(2 k ) over the field where the two operands are element-wise. The two parallel inputs 105a, 105b and the parallel output 105c are k bits wide, ie each consists of k bits.

[0053] In other embodiments, the finite field multiplication subcircuit 105 may be replaced by circuitry for performing other finite field arithmetic, such as multiplicative inversion or exponentiation (eg, squaring) operations. For example, in some embodiments, finite field multiplication subcircuit 105 may be replaced by circuitry for performing arithmetic other than finite field arithmetic (eg, two's complement binary arithmetic).

[0054] In a first embodiment, the circuit 100...

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Abstract

An error-correcting circuit comprises: a component arranged to generate a first output from a first input and a second input; an error detector arranged to generate an error flag indicative of whether or not it has detected an error in the first output, based on the first output,the first input and the second input; a correction generator suitable for generating a correcting output after a first time period beginning with a timing event, based on the first output, the first input and the second input; and an output generator arranged to generate an output of the error-correcting circuit after a second time period beginning with the timing event. If the error flag indicates that an error has been detected in the first output then the second time period may be longer than the first time period, otherwise the second time period may be not longer than the first time period.; If the error flag indicates that an error has been detected in the first output then the output of the error-correcting circuit may comprise a combination of the first output and the correcting output whereby the error detected in the first output is corrected, otherwise the output of the error-correcting circuit may correspond directly to the first output.

Description

technical field [0001] The present invention relates to error correction. Its application is in the design of fault-tolerant circuits, for example in circuits for performing arithmetic operations, but also in other types of circuits. Aspects of the invention also have application in other areas in communications and memory design, such as error correction. Background technique [0002] Modern digital circuits are becoming larger and more complex, and thus more susceptible to errors for a variety of reasons. For example, the reduced size of circuits, and the reduced voltages used to represent data, often increase the likelihood of errors. Errors can occur, for example, due to energetic particles in the environment where the circuit is used causing bit flips in the circuit, or simply due to manufacturing errors. Furthermore, deliberate attempts to introduce errors into circuits by bombarding circuits with energetic particles are increasingly becoming a source of errors, esp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
CPCG06F11/1412G06F11/1048H03M13/15G06F11/1402H04L1/0057G06F11/10H03M13/09
Inventor M·波拉卡帕拉姆贝尔A·贾比尔J·马修D·K·普拉丹
Owner OXFORD BROOKES UNIVERSITY
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